Question

急：VHDL设计八位移位寄存器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHEFT IS
PORT(CLK,M,CO:IN STD_LOGIC;
S:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
QB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CN:OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE BEHAV OF SHEFT IS
SIGNAL ABC:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
ABC<=S&M;
PROCESS(CLK,ABC,CO)
VARIABLE REG8:STD_LOGIC_VECTOR(8 DOWNTO 0);
VARIABLE CY:STD_LOGIC;
BEGIN
IF CLK'EVENT AND CLK='1' THEN
-- IF ABC="000" OR ABC="001" THEN
-- REG8:=REG8;
-- END IF;
IF ABC="010" THEN
CY:=REG8(8);
REG8(8 DOWNTO 1):=REG8(7 DOWNTO 0);
REG8(0):=CY;
END IF;
IF ABC="011" THEN
REG8(0):=CO;
REG8(8 DOWNTO 1):=REG8(7 DOWNTO 0);
CY:=REG8(8);
CO:=CY;
END IF;
IF ABC="100" THEN
CY:=REG8(0);
REG8(6 DOWNTO 0):=REG8(7 DOWNTO 1);
REG8(7):=CY;
END IF;
IF ABC="101" THEN
REG8(8):=CO;
REG8(7 DOWNTO 0):=REG8(8 DOWNTO 1);
CY:=REG8(0);
CO:=CY;
END IF;
IF ABC="110" OR ABC="111" THEN
REG8(7 DOWNTO 0):=D(7 DOWNTO 0);
END IF;
QB(7 DOWNTO 1)<=REG8(7 DOWNTO 1);
END IF;
QB(7 DOWNTO 0)<=REG8(7 DOWNTO 0);
CN<=REG8(8);
END PROCESS;
END BEHAV;
这是源程序，编译时总会提示有一个错误，但是怎么改正呢？

Answer 1

LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SHEFT IS
PORT(CLK,CLR,D:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(0 TO 7));
END ENTITY;

ARCHITECTURE BEHAV OF SHEFT IS
BEGIN
PROCESS(CLK,CLR)
BEGIN
IF CLR='0' THEN
Q<="00000000";
ELSIF CLK'EVENT AND CLK='1' THEN
Q(0)<=D;
Q(1 TO 7)<=Q(0 TO 6);
END IF;
END PROCESS;
END BEHAV;

Answer 2

CO:=CY;

2处试图对IN信号赋值，不可以的

(才看到，来的急么)