Question

16bit ALU VHDL 代码，这样写的对吗？芯片是spartan3

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity alu4 is
port(
Clk :in std_logic;
A,B : in signed (15 downto 0); ---input operands
Op : in unsigned(3 downto 0); ---operation
R : out signed (15 downto 0)); ---output results
end alu4;

architecture Behavioral of alu4 is
signal Reg1, Reg2, Reg3 : signed ( 15 downto 0 ) := (others => '0');
signal tmp : integer := 0;
begin
Reg1 <= A;
Reg2 <= B;
R <= Reg3;
tmp <= conv_integer(B);
process(Clk)
begin
if(rising_edge(clk)) then
case op is
when "0000" =>
Reg3 <= Reg1 + Reg2; ---addition
when "0001" =>
Reg3 <= Reg1 - Reg2;
when "0010" =>
Reg3 <= not Reg1;
when "0011" =>
Reg3 <= Reg1 nand Reg2;
when "0100" =>
Reg3 <= Reg1 nor Reg2;
when "0101" =>
Reg3 <= Reg1 and Reg2;
when "0110" =>
Reg3 <= Reg1 or Reg2;
when "0111" =>
Reg3 <= Reg1 xor Reg2;
when "1000" =>
Reg3 <= Reg1 sll 1; ---shift left sll
when "1001" =>
Reg3 <= Reg1 sla 1; ---shift left sla
when "1010" =>
Reg3 <= Reg1 srl 1; ---shift right srl
when "1011" =>
Reg3 <= Reg1 sra 1; ---shift right sra
when others =>
NULL;
end case;
end if;
end process;
end Behavioral;
出错

Answer 1

1). use ieee.std_logic_signed.all;和use ieee.std_logic_unsigned.all;这两个程序包只能选择其中一个。
2). tmp <= conv_integer(B);这一句没有被用到，因此signal tmp : integer := 0;也没有用处。
3). sll、sla、srl和sra是什么函数？在哪个程序包中预定义过？好像use ieee.std_logic_signed.all;和use ieee.std_logic_unsigned.all;这两个程序包中只有SHR和SHL两个函数。