Question

EDA的VHDL程序：彩灯控制器，共16个彩灯，每次顺序点亮相邻四个彩灯，如此循环执行，循环方向可控制

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity caideng is
port(clk,reset:in std_logic;
l_r:in std_logic; ----控制循环方向；
output:out std_logic_vector(15 downto 0));---输出
end entity;
architecture art of caideng is
signal q:std_logic_vector(15 downto 0);
signal clk_data:std_logic;
begin
process(clk,reset)-----时钟分频，分频因子等于系统时钟频率除以所要得到的时钟频率
variable cnt:integer;
begin
if reset='1' then
cnt:=0;clk_data<='0';
elsif clk'event and clk='1' then
if cnt=4000000 then
cnt:=0;clk_data<='1';
else clk_data<='0';cnt:=cnt+1;
end if;
end if;
end process;
process(clk_data,reset,l_r,q)
begin
if reset='1' then
q<="0000000000000000";
elsif clk_data'event and clk_data='1' then
if l_r='1' then ----表示向右循环；
if q="0000000000000000" then
q<="1111000000000000";
else q<=q(0)&q(15 downto 1);
end if;
else ----向左循环;
if q="0000000000000000" then
q<="0000000000001111";
else q<=q(14 downto 0)&q(15);
end if;
end if;
end if;
output<=q;
end process;
end art;

Answer 2

library ieee;
use ieee.std_logic_1164.all;
entity caideng is
port(clk, rst: in std_logic;
dout: out std_logic_vector(15 downto 0));
end caideng;
architecture rtl of caideng is
signal shift_reg: std_logic_vector(15 downto 0);
begin
process(rst, clk)
begin
if rst = '1' then
shift_reg <= "1111000000000000";
elsif clk'event and clk = '1' then
if dir = '1' then
shift_reg <= shift_reg(14 downto 0) & shift_reg(15);
else
shift_reg <= shift_reg(0) & shift_reg(15 downto 1);
end if;
end if;
end process;
dout <= shift_reg;
end rtl;