Question

60进制减法计数器的VHDL描述

急……

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY subcnt60 IS
PORT(clk,reset: IN STD_LOGIC;
co: OUT STD_LOGIC;
qh,ql: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END subcnt60;
ARCHITECTURE behave OF subcnt60 IS
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk='1' )THEN
IF reset='1' THEN
qh<="0000"; ql<毕梁="0000";
ELSIF qh="0000" and ql="0000" then
qh<="手凯运0101";ql<="1001";co<=’1’;
ELSIF(ql="0000")THEN
ql<="1001";qh<孙拆=qh-1;
ELSE ql<=ql-1; co<=’0’;
END IF;
END IF;
END PROCESS;
END behave;

Answer 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_60 is
port(clk,reset:in std_logic;
load:in std_logic;
current_value:in std_logic_vector(5 downto 0);
output:out std_logic_vector(5 downto 0));
end entity;
architecture art of count_60 is
begin
process(clk,reset,load,current_Value)
variable cnt:std_logic_vector(5 downto 0);
begin
if reset='慧大1' then
cnt:="友碧芦111100";
elsif clk'event and clk='好带1' then
if load='1' then
cnt:=current_value;
else cnt:=cnt-1;
end if;
end if;
output<=cnt;
end process;
end art;

Answer 3

这还要急、。。。。
百度一下，多的很哦