Question

求助：一个简单的verilog程序，仿真了后有些问题，在线等

module chuangxinjijin(
clk_50M,rst_n,
count1,count2,
SP
);
input clk_50M,rst_n;
output reg [16:0] count1;
output reg [14:0] count2;

output reg SP;

//-----------------------------SP-------------------------------------

reg clear;
always @(negedge clk_50M or negedge rst_n)
if(!rst_n)
count1 <= 1'b0;
else if(count1==59996 )
begin
clear <= 1;
count1 <= 1'b0;
end
else
begin
count1 <= count1 + 1'b1;
clear <= 0;
end

//--------------------------------------------------------------
always @(negedge clk_50M or negedge rst_n)
if(!rst_n)
count2 <= 1'b0;
else if(coun2>=0 && count2<281)
begin
SP <= 1'b0;
count2 <= count2 + 1'b1;
end
else if(count2>=281 && count2<286 )
begin
SP <= 1'b1;
count2 <= count2 + 1'b1;
end
else if(count2>=286 && count2<330)
begin
SP <= 1'b0;
count2 <= count2 + 1'b1;
end
else if (count2 == 330)
count2 <= 281;
else if (clear == 1)
count2 <= 0;
else
count2 <= count2 + 1'b1;

endmodule
问题如下，为什么在clear为1，也就四count1计数到59996时，count2不为0哇

Answer 1

你这代码count2没错的话应该一直在281到330之间循环，进入死循环了，else if (count2 == 330)
count2 <= 281;这个条件一满足就跳回去了，不会执行到else if (clear == 1)
count2 <= 0;这一步的。可以把这条语句放到复位语句的后面，试试应该就可以了
if(!rst_n)
count2 <= 1'b0;
else if (clear == 1)
count2 <= 0；
else if(coun2>=0 && count2<281)
begin
SP <= 1'b0;
count2 <= count2 + 1'b1;
end
。。。

Answer 2

条件写的有问题，轮不到执行clear ==1. count2 加到330 变成281，符合else if(count2>=281 && count2<286 )这个条件就不会往后面执行了，所以你这是一个死循环。