Question

求FPGA高手解释：为什么以下在quartus2中编译后，逻辑单元为0且仿真没有结果？

module bcd_decoder(i,y);
input[3:0]i;
output[7:0]y;
reg[7:0]y;
always
begin
case(i)
4`b0000:y[7:0]=8`b11111100;
4`b0001:y[7:0]=8`b01100000;
4`b0010:y[7:0]=8`b11011010;
4`b0011:y[7:0]=8`b11110010;
4`b0100:y[7:0]=8`b01100110;
4`b0101:y[7:0]=8`b10110110;
4`b0110:y[7:0]=8`b10111110;
4`b0111:y[7:0]=8`b11100000;
4`b1000:y[7:0]=8`b11111110;
4`b1001:y[7:0]=8`b11110110;
4`b1010:y[7:0]=8`b11101110;
4`b1011:y[7:0]=8`b00111110;
4`b1100:y[7:0]=8`b10011100;
4`b1101:y[7:0]=8`b01111010;
4`b1110:y[7:0]=8`b10011110;
4`b1111:y[7:0]=8`b10001110;
default:y[7:0]=8`b11111111;
endcase
end
endmodule
编译确保已经通过了，就是没有逻辑单元，我试了一下二选一的选择器的设计，也没用到逻辑单元，但是仿真却是真确的，所以郁闷的是到底没有逻辑单元是不是个错误？

Answer 1

你确定在Quartus II中编译没有错误吗？你的字母b前的那个符号都不对，比如4`b0000中那个撇就不对，改正确之后就能编译通过了，应该是用了7个逻辑单元。
至于楼上那英文说的你没有时钟的问题，如果你不是时序逻辑，只是组合逻辑，没有时钟当然没有问题；那不是一个错误。按你这个代码来说，没有时钟，就是纯粹的组合逻辑。

Answer 2

of course it will not get any synthesized logic as no sensitive list with always statement.
a clock signal is necessary. try
input clock;
always@(posedge clock)
---------------------------------------
they are right, replace all of your ` with ' and you will get the result you expect.
btw, i have run your code on Quartus 9.1 sp1, and it DOES say "no clocks defined in design". so what it means is, at least you should use a register to store your result IN THIS DESIGN.

Answer 3

4'b和8'b中间哪个是单引号，不是TAB键上面那个`

Answer 4

楼上说得有道理，确保编译通过后，仿真前需要设置输入波形，仿真后才会有输出波形