Question

请设计一位二进制全加器组合逻辑电路。。

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add1 is
port(a,b,cin:in std_logic;
co,s:out std_logic);
end add1;
architecture behave of add1 is
begin
process(a,b,cin)
variable n:integer range 0 to 3;
constant s_vector:
std_logic_vector(0 to 3):="1010";
constant co_vector:
std_logic_vector(0 to 3):="1100";
begin
n:=0;
if(a='1')then n:=n+1;
end if;
if(b='1')then n:=n+1;
end if;
if(cin='1')then n:=n+1;
end if;
s<=s_vector(n);
co<=co_vector(n);
end process;
end behave;

Answer 2

http://baike.baidu.com/view/549297.htm

Answer 3

这位仁兄，是在做电子技术实验课吧。。。