Question

i5-520E i5-520m

i5-520E i5-520m的区别

Answer 1

520M是i5处理器的其中一个型号，i5还有i5-540M i5-430M等，i5处理器是双核四线程 支持睿频加速技术，很不错的一款处理器。

这个与以前的那些处理器的表示方式是差不多的！ 譬如以前的就区分T3、T4、T5、T6、P7、P8等系列，而具体型号就是T4（数字）XX0中的XX。 而i5-520M中，i5是表示系列，520是具体型号，M说明是移动处理器。

芯片评价

面对着价格昂贵的Core i7，新架构处理器很难走进广大消费者的生活之中，不过曝光了又一款基于Nehalem架构的双核处理器，其依旧采用整合内存控制器，三级缓存模式，L3达到8MB，支持Turbo Boost等技术的新处理器——Core i5酷睿I5。

Core i5 采用的是成熟的DMI（Direct Media Interface），相当于内部集成所有北桥的功能，采用DMI用于准南桥通信，并且只支持双通道的DDR3内存。结构上它用的是LGA1160（后改为LGA1156）接口，Core i7用的是LGA1366。

Answer 2

详细信息都在下面了，自己慢慢看其中区别！

Model number ? I5-520M
CPU part number CN80617004119AE (SLBNA)
Frequency (MHz) ? 2400
Turbo frequency (MHz) 2933 (1 core)
2667 (2 cores)
Low power frequency (MHz) 1200
Clock multiplier ? 18
Package 1288-ball micro-FCBGA10
Size 1.34" x 1.1" / 3.4cm x 2.8cm
Introduction date January 7, 2010
Price at introduction $225

Architecture / Microarchitecture
Microarchitecture Nehalem (Westmere)
Platform Calpella
Processor core ? Arrandale
Core stepping ? C2 (SLBNA)
Manufacturing process 0.032 micron
382 million transistors (CPU die)
177 million transistors (IMC / graphics die)
Die size 81 (CPU die)
114 (IMC / graphics die) mm2

Data width 64 bit
Number of cores 2
Floating Point Unit Integrated
Level 1 cache size ? 2 x 32 KB instruction caches
2 x 32 KB data caches
Level 2 cache size ? 2 x 256 KB
Level 3 cache size 3 MB
Multiprocessing Not supported
Features MMX instruction set
SSE
SSE2
SSE3
Supplemental SSE3
SSE4.1 ?
SSE4.2 ?
AES instructions
EM64T technology ?
Hyper-Threading technology ?
Turbo Boost technology ?
Execute Disable bit ?
Virtualization technology (VT-x and VT-d)
Trusted Execution Technology

Low power features Thread C1, C3 and C6 states
Core C1/C1E, C3 and C6 states
Package C1/C1E, C3 and C6 states
Enhanced SpeedStep technology ?

On-chip peripherals Integrated dual-channel DDR3 SDRAM Memory controller
Direct Media Interface
Integrated HD graphics controller

Electrical/Thermal parameters
V core (V) ? 0.8 - 1.4 (High Frequency mode)
0.775 - 1 (Low Frequency mode)
Minimum/Maximum operating temperature (°C) ? 0 - 105
Maximum power dissipation (W) ? 3.8 (TDP in C6 state) / 67.2 (peak, CPU core only)
44.8 (sustained, CPU core only)
Thermal Design Power (W) ? 35 (Package)
25 (CPU core)
12.5 (Graphics core)

Model number ? I5-520E
CPU part number CN80617004461AB (SLBP6)
Frequency (MHz) ? 2400
Clock multiplier ? 18
Package 1288-ball micro-FCBGA10
Size 1.34" x 1.1" / 3.4cm x 2.8cm
Introduction date January 7, 2010
Price at introduction $225

Architecture / Microarchitecture
Microarchitecture Nehalem (Westmere)
Platform Calpella
Processor core ? Arrandale
Core stepping ? C2 (SLBP6)
Manufacturing process 0.032 micron
382 million transistors (CPU die)
177 million transistors (IMC / graphics die)
Die size 81 (CPU die)
114 (IMC / graphics die) mm2

Data width 64 bit
Number of cores 2
Floating Point Unit Integrated
Level 1 cache size ? 2 x 32 KB instruction caches
2 x 32 KB data caches
Level 2 cache size ? 2 x 256 KB
Level 3 cache size 3 MB
Multiprocessing Not supported
Features MMX instruction set
SSE
SSE2
SSE3
Supplemental SSE3
SSE4.1 ?
SSE4.2 ?
AES instructions
EM64T technology ?
Hyper-Threading technology ?
Turbo Boost technology ?
Execute Disable bit ?
Virtualization technology (VT-x and VT-d)
Trusted Execution Technology

Low power features Thread C1, C3 and C6 states
Core C1/C1E, C3 and C6 states
Package C1/C1E, C3 and C6 states
Enhanced SpeedStep technology ?

On-chip peripherals Integrated dual-channel DDR3 SDRAM Memory controller
Direct Media Interface
Integrated HD graphics controller

Electrical/Thermal parameters
V core (V) ? 0.8 - 1.4 (High Frequency mode)
0.775 - 1 (Low Frequency mode)
Minimum/Maximum operating temperature (°C) ? 0 - 105
Maximum power dissipation (W) ? 3.8 (TDP in C6 state) / 67.2 (peak, CPU core only)
44.8 (sustained, CPU core only)
Thermal Design Power (W) ? 35 (Package)
25 (CPU core)
12.5 (Graphics core)