Question

初学modelsim，有一段VHDL代码，怎么给这段代码写testbench

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY choice IS
PORT( nextt:IN STD_LOGIC;
start:IN STD_LOGIC;
s1,s2,s3:OUT INTEGER RANGE 0 TO 3;
led:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END choice;
ARCHITECTURE bodyofchoice OF choice IS
TYPE choice_state IS (A,B,C,D,E);
SIGNAL cs:choice_state;
BEGIN
P1:PROCESS(nextt)
BEGIN
IF(nextt'EVENT AND nextt='1') THEN
IF start='0' THEN
CASE cs IS
when A=> s1<=1;s2<=0;s3<=0;led<="100";cs<=B;
when B=> s1<=2;s2<=0;s3<=0;led<="010";cs<=C;
when C=> s1<=3;s2<=0;s3<=0;led<="001";cs<=D;
when D=> s1<=2;s2<=3;s3<=0;led<="011";cs<=E;
when E=> s1<=1;s2<=2;s3<=3;led<="111";cs<=A;
when others=>null;
END CASE;
END IF;
END IF;
END PROCESS P1;
END bodyofchoice;

Answer 1

需要什么样的激励可以自己改，没有测试，你自己试一下。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity testbench is --一个空的实体，没有输入和输出。
end testbench;

architecture one of testbench is
component choice is
port(nextt:IN STD_LOGIC;
start:IN STD_LOGIC;
s1,s2,s3:OUT INTEGER RANGE 0 TO 3;
led:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
end component choice; --被测器件的申明。

signal nextt :std_logic:='0';
signal start :std_logic:='1';
signal s1,s2,s3: std_logic;
signal led: std_logic_vector(3 downto 0); --所要信号的申明

constant clk_period :time :=20 ns;
begin
U1: choice port map(
nextt => nextt,
start => start,
s1 => s1,
s2 => s2,
s3 => s3,
led => led); --进行信号的匹配

clkProcess: --nextt激励（时钟）
process
begin
wait for clk_period/2;
nextt <= '1';
wait for clk_period/2;
nextt <= '0';
end process;

startProcess: process --start激励
begin
start<='1';
wait for 300ns;
start<='0';
wait;
end process ClockProcess;

Answer 2

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