Question

用VHDL语言设计一个电子时钟

用VHDL语言设计一个电子时钟 1）能实现24小时、60分、60秒的基本计时功能，可以通过按键设置和调整时间，并通过数码管显示时间 24小时制显示当前时间：小时用8与7数码管，分钟用5与4位数码管，秒由2与1位数码管表示，小时与分钟之间、分钟与秒之间用3和6位数码管显示“—”，总计八位七段数码显示管。此模式下显示当前时间。
（2）系统组成可分为FPGA内部电路和外围电路两个部分。设计的主要任务是FPGA内部各个电路模块的设计、仿真和验证等。
（3）FPGA内部包括底层模块和顶层电路模块的设计。底层模块大致包括：计时电路、时间设置（预置时间）和译码电路等，底层模块要求采用VHDL语言完成设计；顶层模块可采用VHDL语言或其它设计输入方法。
（4）FPGA端口包括按键和数码管信号。按键主要完成复位和时间设置（预置）等功能；显示电路采用LED数码管完成时、分、秒的显示。
（1）时间显示模式：
24小时制显示当前时间：小时用8与7数码管，分钟用5与4位数码管，秒由2与1位数码管表示，小时与分钟之间、分钟与秒之间用3和6位数码管显示“—”，总计八位七段数码显示管。此模式下显示当前时间。
（2）校时模式：
将time键置于‘0’，运用功能键set键对八位数码管进行选择，并由功能键up键进行+1与down键进行-1操作，通过此4个功能键进行校时设置。
Set->数码管7-> Set->数码管6-> Set->数码管5-> Set->数码管4-> Set->数码管3-> Set->数码管2-> Set->数码管1
Up->+1;down->-1;
（3）闹钟设定模式：
将time键置于‘1’，设定模式与校时时设定一样，运用功能键set键对八位数码管进行选择，并由功能键up键进行+1与down键进行-1操作，通过此4个功能键进行校时设置。
Set->数码管7-> Set->数码管6-> Set->数码管5-> Set->数码管4-> Set->数码管3-> Set->数码管2-> Set->数码管1
Up->+1;down->-1;

Answer 1

秒计时模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port (clk,reset,setmin:in std_logic;
enmin:out std_logic;
dh:buffer std_logic_vector (3 downto 0);
dl:buffer std_logic_vector (3 downto 0);
end;
architecture beha of second is
begin
process(clk,reset,setmin)
bigin
if setmin='0' then
enmin<=clk;
elsif dl="1001" and dh="0101" then
enmin<='0';
else
enmin<='1';
end if;
if reset='0' then
dh<="0000";
dl<="0000";
elsif (clk'event and clk='1') then
if dl=9 then
dl<="0000";
if dh=5 then
dh<="0000";
else
dh<=dh+1;
end if;
else
dl<=dl+1;
end if;
end if;
end process;
end;
分计时模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minute is
port (clk,clk1,reset,sethour:in std_logic;
enhour:out std_logic;
dh:buffer std_logic_vector (3 downto 0);
dl:buffer std_logic_vector (3 downto 0);
end;
architecture beha of minute is
begin
process (clk,clk1,reset,sethour)
begin
if sethour='0' then
enhour<=clk1;
elsif dl="1001" and dh="0101" then
enhour<='0';
else
enhour<='1';
end if;
if reset='0' then
dh<="0000";
dl<="0000";
elsif (clk'event and clk='1') then
if dl=9 then
dl<="0000";
if dh=5 then
dh<="0000";
else
dh<=dh+1;
end if;
else
dl<=dl+1;
end if;
end if;
end process;
end;
时计时模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is
port (clk,reset:in std_logic;
dh:buffer std_logic_vector (3 downto 0);
dl:buffer std_logic_vector (3 downto 0);
end;
architecture beha of hour is
begin
process (clk,reset)
begin
if reset='0' then
dh<="0000";
dl<="0000";
elsif (clk'event and clk='1') then
if dh="0010" and dl="0011" then
dl<="0000";
dh<="0000";
elsif dl=9 then
dl<="0000";
if dh=2 then
dh<="0000";
else
dh<=dh+1;
end if;
end if;
end process;
end;
轮流显示模块
library ieee;
use ieee.std_logic_1164.all;
entity lunliu1 is
port (sech,secl,minh,minl,hourh,hourl:in std_logic_vector (3 downto 0);
clk:in std_logic;
q:buffer std_logic_vector (5 downto 0);
dout:out std_logic_vector (3 downto 0));
end;
architecture beha of lunliu1 is
signal qin: integer range 5 downto 0;
begin
process (clk)
begin
if (clk'event and clk='1') then
if qin>=5 then
qin<=0;
else
qin<=qin+1;
end if;
end if;
if qin=0 then
dout<=secl (3 downto 0);
q<="111110";
elsif qin=1 then
dout<=sech (3 downto 0);
q<="111101";
elsif qin=2 then
dout<=minl (3 downto 0);
q<="111011";
elsif qin=3 then
dout<=minh (3 downto 0);
q<="110111";
elsif qin=4 then
dout<=hourl (3 downto 0);
q<="101111";
elsif qin=5 then
dout<=hourh (3 downto 0);
q<="011111";
end if;
end process;
end;
译码模块
library ieee;
use ieee.std_logic_1164.all;
entity xianshi is
port (num:in std_logic_vector (3 downto 0);
led8:out std_logic_vector (7 downto 0));
end;
architecture beha of xianshi is
begin
process (num)
begin
case num is
when "0000"=>led8<="11000000";
when "0001"=>led8<="11111001";
when "0010"=>led8<="10100100";
when "0011"=>led8<="10110000";
when "0100"=>led8<="10011001";
when "0101"=>led8<="10010010";
when "0110"=>led8<="10000010";
when "0111"=>led8<="11111000";
when "1000"=>led8<="10000000";
when "1001"=>led8<="10010000";
when others=>null;
end case;
end process;
end;
报时信号产生模块
library ieee;
use ieee.std_logic_1164.all;
entity speak is
port (clk,hour:in std_logic;
speak:out std_logic);
end;
architecture beha of speak is
begin
process (hour)
begin
if (hour'event and hour=1) then
speak<=clk;
end if;
end process;
end;

Answer 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shuzizhong is
port(clk,,clk1,set,change,s1,s2,s3:in std_logic;
second1,second2,minite1,minite2,hour1,hour2:out std_logic_vector(3 downto 0);
Light:out std_logic_vector(7 downto 0);
cout:out std_logic);
end entity;
architecture one of shuzizhong is
begin
pro1:process(clk,set,s1,s2,s3,change)
variable msecond1,msecond2,mminite1,mminite2,mhour11,mhour12,mhour21,mhour22:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then

if set='1' then -----启动校验
if s1='1'
then msecond1:=msecond1+1;
if msecond1="1010"
then msecond1:="0000";
msecond2:=msecond2+1;
if msecond2="0110"
then msecond2:="0000";
end if;
end if;
end if; --------秒校验
if s2='1'
then
mminite1:=mminite1+1;
if mminite1="1010"
then mminite1:="0000";
mminite2:=mminite2+1;
if mminite2="0110"
then mminite2:="0000";
end if;
end if;
end if; ---------分校验
if s3='1' then
mhour11:=mhour11+1;
mhour21:=mhour21+1;
if mhour11="1010" then mhour11:="0000";
mhour12:=mhour12+1;
end if;
if mhour11="0011" and mhour12="0001"
then mhour11:="0001";mhour12:="0000";
end if;
if mhour21="1010" then mhour21:="0000";
mhour22:=mhour22+1;
end if;
if mhour21="0100"and mhour22="0010"
then mhour21:="0000";mhour22:="0000";
end if;
end if;-------时校验
else msecond1:=msecond1+1;-----正常计时工作
if msecond1="1010"
then msecond1:="0000";
msecond2:=msecond2+1;
if msecond2="0110"
then msecond2:="0000";
mminite1:=mminite1+1;
if mminite1="1010"
then mminite1:="0000";
mminite2:=mminite2+1;
if mminite2="0110"
then mminite2:="0000";
mhour11:=mhour11+1;
mhour21:=mhour21+1;
if mhour11="1010" then mhour11:="0000";
mhour12:=mhour12+1;
end if;
if mhour11="0011" and mhour12="0001"
then mhour11:="0001";mhour12:="0000";
end if;-------12小时制
、 if mhour21="1010" then mhour21:="0000";
mhour22:=mhour22+1;
end if;
if mhour21="0100"and mhour22="0010"
then mhour21:="0000";mhour22:="0000";
end if;----------24小时制

end if;
end if;
end if;
end if;
end if;
second1<=msecond1;
second2<=msecond2;
minite1<=mminite1;
minite2<=mminite2;
if change='0' then hour1<=mhour11;hour2<=mhour12;
else hour1<=mhour21;hour2<=mhour22;------12/24小时制转换
end if;
if clk1'event and clk1='1' then
if (msecond1<"0000") and (msecond2="0000") and (mminite1="0000") and (mminite2="0000")
then cout<=clk;
else cout<='0';
end if;-----------整点报时
end if;
if msecond1="0000" then Light="00011000" end if;
if msecond1="0001" then Light="00100100" end if;
if msecond1="0010" then Light="01000010" end if;
if msecond1="0011" then Light="10000001" end if;
if msecond1="0100" then Light="01000010" end if;
if msecond1="0101" then Light="00100100" end if;
if msecond1="0110" then Light="00011000" end if;
if msecond1="0111" then Light="00100100" end if;
if msecond1="1000" then Light="01000010" end if;
if msecond1="1001" then Light="10000001" end if;
end if;

end process;

end architecture one;---------