Question

VHDL语言写程序出现Error。。。

Error (10818): Can't infer register for "lock_1" at ctrl.vhd(24) because it does not hold its value outside the clock edge
源程序如下，请问应该如何改正
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ctrl is
port(
set,check,close,back,clk: in std_logic;
dn: in std_logic_vector(3 downto 0);
sout: out std_logic_vector(23 downto 0);
lock: out std_logic);
end ctrl;

architecture beh of ctrl is
signal ch:std_logic;
begin
process(clk,dn)
variable lock_1:std_logic;
variable acc:std_logic_vector(23 downto 0);
variable temp1,temp2,temp3,temp4,temp5,temp6:std_logic_vector(3 downto 0);

begin
ch<=not(dn(0) and dn(1) and dn(2) and dn(3));
lock_1:='0';

if clk'event and clk='1' then 错误显示在这里
if ch='1' then
temp6:=temp5;
temp5:=temp4;
temp4:=temp3;
temp3:=temp2;
temp2:=temp1;
temp1:=dn;
end if;

if back='1' then
temp1:=temp2;
temp2:=temp3;
temp3:=temp4;
temp4:=temp5;
temp5:=temp6;
temp6:="0000";
lock_1:='0';
end if;

if set='1' then
acc:=temp6&temp5&temp4&temp3&temp2&temp1;
lock_1:='0';
end if;

if check='1' then
if acc=temp6&temp5&temp4&temp3&temp2&temp1 then lock_1:='1';
elsif temp6&temp5&temp4&temp3&temp2&temp1="100010001000100010001000" then
lock_1:='1';
end if;
end if;

if close ='1' then
lock_1:='0';
temp1:="0000";
temp2:="0000";
temp3:="0000";
temp4:="0000";
temp5:="0000";
temp6:="0000";
end if;
end if;

sout<=temp6&temp5&temp4&temp3&temp2&temp1;
lock<=lock_1;
end process;
end beh;

Answer 1

if else没有匹配好，后面的光有else没有if，而且你的程序是按C语言的思路编的，这么多if也很容易弄混，用case比较好些。例如：IF (CHOS="0010") THEN IF POINTS_B1="1001" THEN else POINTS_B1:="0000";POINTS_B2:=POINTS_B2+"0001"; IF POINTS_B2="1001" THEN POINTS_B2:="0000"; else POINTS_B1:=POINTS_B1+"0001";END IF;end if; if在哪？

追问

....并没有用else