Question

关于VHDL语言的填空，求高人

LIBRARY IEEE;USE IEEE,STD_LOGIC,1164 ALL;
USE IEEE________ALL;
ENTTTY CNT IS
______CCLK;IN STD_LOGIC;Y:OUT_______
(3 DOWNTO 0);
END CNT;
ARCHITECTURE One OF_______IS
SIGNAL Qq:STD_LOGIC_VECTOR(3 DOWNTO 0);
BECIN
PROCESS(CLK)
_______
IF vising_edg e(CLK) THEN-上升沿检测
IF Qq>q THEN
________________; 清零
ELSE
Qq<=_______;-加一
END IF;
___________;
ND PROCESS;
——————
END ONE;

求大神

Answer 1

std_logic_unsigned
port
CNT

begin
Qq<="0000"
Qq+1
end if
Y=Qq