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/** @file API.h
*
* @author Runar Kjellhaug
*
* @compiler This program has been tested with Keil C51 V7.50.
*
*
* $Date: 31.01.06 14:14 $
* $Revision: 13 $
*
*/
// Macro to read SPI Interrupt flag
#define WAIT_SPIF (!(SPI0CN & 0x80)) // SPI interrupt flag(礐 platform dependent)
// Declare SW/HW SPI modes
#define SW_MODE 0x00
#define HW_MODE 0x01
#define BYTE unsigned char
// Define nRF24L01 interrupt flag's
#define IDLE 0x00 // Idle, no interrupt pending
#define MAX_RT 0x10 // Max #of TX retrans interrupt
#define TX_DS 0x20 // TX data sent interrupt
#define RX_DR 0x40 // RX data received
#define SPI_CFG 0x40 // SPI Configuration register value
#define SPI_CTR 0x01 // SPI Control register values
#define SPI_CLK 0x00 // SYSCLK/2*(SPI_CLK+1) == > 12MHz / 2 = 6MHz
#define SPI0E 0x02 // SPI Enable in XBR0 register
//********************************************************************************************************************//
// SPI(nRF24L01) commands
#define READ_REG 0x00 // Define read command to register
#define WRITE_REG 0x20 // Define write command to register
#define RD_RX_PLOAD 0x61 // Define RX payload register address
#define WR_TX_PLOAD 0xA0 // Define TX payload register address
#define FLUSH_TX 0xE1 // Define flush TX register command
#define FLUSH_RX 0xE2 // Define flush RX register command
#define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
//#define NOP 0xFF // Define No Operation, might be used to read status register
//********************************************************************************************************************//
// SPI(nRF24L01) registers(addresses)
#define CONFIG 0x00 // 'Config' register address
#define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
#define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
#define SETUP_AW 0x03 // 'Setup address width' register address
#define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
#define RF_CH 0x05 // 'RF channel' register address
#define RF_SETUP 0x06 // 'RF setup' register address
#define STATUS 0x07 // 'Status' register address
#define OBSERVE_TX 0x08 // 'Observe TX' register address
#define CD 0x09 // 'Carrier Detect' register address
#define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
#define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
#define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
#define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
#define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
#define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
#define TX_ADDR 0x10 // 'TX address' register address
#define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
#define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
#define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
#define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
#define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
#define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
#define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
/*********************************************************************************************/
/*********************************************************************************************/
/*********************************************************************************************/
/*********************************************************************************************/
/*********************************************************************/
/* CE(PD4) CSN(PD5) SCK(PB7) MOSI(PB5) MISO(PB6) IRQ(PD2) */
/*********************************************************************/
#define TX_ADR_WIDTH 5
#define TX_PLOAD_WIDTH 32 //缓冲区大小
#define CE_0 do {PORTD&=0xEF;} while(0)
#define CE_1 do {PORTD|=0x10;} while(0)//PD4
#define CSN_0 do {PORTD&=0XDF;} while(0)
#define CSN_1 do {PORTD|=0X20;} while(0)//PD5
unsigned char TX_ADDRESS[TX_ADR_WIDTH]={0x00,0x00,0x90,0x34,0xA7}; // Define a static TX address
unsigned char rx_buf[TX_PLOAD_WIDTH]; //RX缓冲区
unsigned char tx_buf[TX_PLOAD_WIDTH]; //TX缓冲区
volatile unsigned char flag,date,sta;
void spi_init()
{
DDRB|=0XB0;//SCK、SS and MOSI
DDRB&=~_BV(PB6);//MISO
SPCR = (1 << SPE)|(1 << MSTR)|(1 << SPR0);
SPSR = 0;
}
unsigned char send_spi(unsigned char date)
{
SPSR &= ~(1 << SPIF);
SPDR=date;
while((SPSR&0X80)==0X00);
return SPDR;
}
void interr_0()
{
DDRD&=~_BV(PD2);
MCUCR=0X02;
SREG|=0X80;
GICR=0X40;
}
void init_sys()
{
DDRD|=0x30;
CE_0;
CSN_0;
}
/**************************************************
Function: SPI_RW_Reg();
Description:
Writes value 'value' to register 'reg'
**************************************************/
unsigned char SPI_RW_Reg(BYTE reg, BYTE value)
{
unsigned char a;
CSN_0;
a=send_spi(reg);
send_spi(value); // ..and write value to it..
CSN_1;
return(a); // return nRF24L01 status byte
}
/**************************************************/
/**************************************************/
BYTE SPI_Read(BYTE reg)
{
BYTE reg_val;
CSN_0;//CSN IS LOW
send_spi(reg); // Select register to read from..
reg_val=send_spi(0); // ..then read registervalue
CSN_1;
return(reg_val); // return register value
}
/**************************************************
Function: SPI_Read_Buf();
Description:
Reads 'bytes' #of bytes from register 'reg'
Typically used to read RX payload, Rx/Tx address
**************************************************/
unsigned char SPI_Read_Buf(BYTE reg, BYTE *pBuf, BYTE bytes)
{
unsigned char status,byte_ctr;
CSN_0;//CSN IS LOW
status=send_spi(reg); // Select register to write to and read status byte
for(byte_ctr=0;byte_ctr<bytes;byte_ctr++)
pBuf[byte_ctr] = send_spi(0); // Perform SPI_RW to read byte from nRF24L01
CSN_1;
return(status);
}
/**************************************************/
/**************************************************
Function: SPI_Write_Buf();
Description:
Writes contents of buffer '*pBuf' to nRF24L01
Typically used to write TX payload, Rx/Tx address
**************************************************/
unsigned char SPI_Write_Buf(BYTE reg, BYTE *pBuf, BYTE bytes)
{
unsigned char status,byte_ctr;
CSN_0;//CSN IS LOW
status=send_spi(reg); // Select register to write to and read status byte
for(byte_ctr=0; byte_ctr<bytes; byte_ctr++) // then write all byte in buffer(*pBuf)
send_spi(*pBuf++);
CSN_1;
return(status);
}
/**************************************************/
void init_24l01()
{
SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x0f); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
}
/**************************************************
Function: RX_Mode();
Description:
This function initializes one nRF24L01 device to
RX Mode, set RX address, writes RX payload width,
select RF channel, datarate & LNA HCURR.
After init, CE is toggled high, which means that
this device is now ready to receive a datapacket.
**************************************************/
void RX_Mode(void)
{
CE_0;
SPI_Write_Buf((WRITE_REG + RX_ADDR_P0), TX_ADDRESS, TX_ADR_WIDTH); //Use the same address on the RX device as the TX device
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..
CE_1; // Set CE
}
/**************************************************
Function: TX_Mode();
Description:
This function initializes one nRF24L01 device to
TX mode, set TX address, set RX address for auto.ack,
fill TX payload, select RF channel, datarate & TX pwr.
PWR_UP is set, CRC(2 bytes) is enabled, & PRIM:TX.
ToDo: One high pulse(>10us) on CE will now send this
packet and expext an acknowledgment from the RX device.
**************************************************/
void TX_Mode(void)
{
CE_0;
SPI_Write_Buf((WRITE_REG + TX_ADDR), TX_ADDRESS, TX_ADR_WIDTH); // Writes TX_Address to nRF24L01
SPI_Write_Buf((WRITE_REG + RX_ADDR_P0), TX_ADDRESS, TX_ADR_WIDTH); // RX_Addr0 same as TX_Adr for Auto.Ack
SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // Writes data to TX payload
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_DS enabled..
_delay_ms(5);
CE_1;
}
/**************************************************/
/* 中断函数 */
/**************************************************/
ISR(INT0_vect)
{
flag=1;
sta=SPI_Read(STATUS); // read register STATUS's value
SPI_RW_Reg(WRITE_REG+STATUS,sta);// clear RX_DR or TX_DS or MAX_RT interrupt flag
if(sta&RX_DR) // if receive data ready (RX_DR) interrupt
{
SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH);// read receive payload from RX_FIFO buffer
}
if(sta&MAX_RT)
{
SPI_RW_Reg(FLUSH_TX,0x00);
}
if(sta&TX_DS)
{
;
}
RX_Mode();
}
/********************************************************************
* 文件名 : ATmega32A_NRF24L01
* 描述 : 发送端
*创建人 :69223856@qq.com
* 日期 : 2010/3/10
* 版本号 : V1.0
* 备注 : 时钟频率8.0MHz
***********************************************************************/
#define F_CPU 8000000UL //8M晶振
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include "2401.h"
#define uchar unsigned char
#define uint unsigned int
/**************************************************/
int main()
{
unsigned char i;
init_sys();
spi_init();
interr_0();
init_24l01();
RX_Mode();
PORTA|=0X02;
DDRA&=0XFD;//PA1输入
while(1)
{
if( (PINA&0x02)==0 )//PA1低电平
{
for(i=1;i<4;i++)
{
tx_buf[0]=i;
TX_Mode();
DDRA|=_BV(PA0);
PORTA|=_BV(PA0);
_delay_ms(500);
}
}
}
}
/********************************************************************
* 文件名 : ATmega32A_NRF24L01
* 描述 : 接收端
* 创建人 :69223856@qq.com
* 日期 : 2010/3/10
* 版本号 : V1.0
* 备注 : 时钟频率8.0MHz
***********************************************************************/
#define F_CPU 8000000UL
#include<avr/io.h>
#include<avr/interrupt.h>
#include<util/delay.h>
#include "2401.h"
#include"5110.h"
#define uchar unsigned char
#define uint unsigned int
/**************************************************/
volatile unsigned char i;
void main()
{
DDRA|=0xF1;
DDRB|=0x04;
LCD_init(); //初始化LCD模块
LCD_clear(); //清屏幕
init_sys();
spi_init();
interr_0();
init_24l01();
RX_Mode();
backled1;
while(1)
{
if(flag==1)
{
i=rx_buf[0];
LCD_PutString12x16(16,16,Put_variable(i) );
if(rx_buf[0]==3)
{
PORTA|=0X01;
DDRA|=0X01;
}
else
PORTA&=~_BV(PA0);
flag=0;
}
}
}
/**************************************************/
*
* @author Runar Kjellhaug
*
* @compiler This program has been tested with Keil C51 V7.50.
*
*
* $Date: 31.01.06 14:14 $
* $Revision: 13 $
*
*/
// Macro to read SPI Interrupt flag
#define WAIT_SPIF (!(SPI0CN & 0x80)) // SPI interrupt flag(礐 platform dependent)
// Declare SW/HW SPI modes
#define SW_MODE 0x00
#define HW_MODE 0x01
#define BYTE unsigned char
// Define nRF24L01 interrupt flag's
#define IDLE 0x00 // Idle, no interrupt pending
#define MAX_RT 0x10 // Max #of TX retrans interrupt
#define TX_DS 0x20 // TX data sent interrupt
#define RX_DR 0x40 // RX data received
#define SPI_CFG 0x40 // SPI Configuration register value
#define SPI_CTR 0x01 // SPI Control register values
#define SPI_CLK 0x00 // SYSCLK/2*(SPI_CLK+1) == > 12MHz / 2 = 6MHz
#define SPI0E 0x02 // SPI Enable in XBR0 register
//********************************************************************************************************************//
// SPI(nRF24L01) commands
#define READ_REG 0x00 // Define read command to register
#define WRITE_REG 0x20 // Define write command to register
#define RD_RX_PLOAD 0x61 // Define RX payload register address
#define WR_TX_PLOAD 0xA0 // Define TX payload register address
#define FLUSH_TX 0xE1 // Define flush TX register command
#define FLUSH_RX 0xE2 // Define flush RX register command
#define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
//#define NOP 0xFF // Define No Operation, might be used to read status register
//********************************************************************************************************************//
// SPI(nRF24L01) registers(addresses)
#define CONFIG 0x00 // 'Config' register address
#define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
#define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
#define SETUP_AW 0x03 // 'Setup address width' register address
#define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
#define RF_CH 0x05 // 'RF channel' register address
#define RF_SETUP 0x06 // 'RF setup' register address
#define STATUS 0x07 // 'Status' register address
#define OBSERVE_TX 0x08 // 'Observe TX' register address
#define CD 0x09 // 'Carrier Detect' register address
#define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
#define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
#define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
#define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
#define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
#define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
#define TX_ADDR 0x10 // 'TX address' register address
#define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
#define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
#define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
#define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
#define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
#define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
#define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
/*********************************************************************************************/
/*********************************************************************************************/
/*********************************************************************************************/
/*********************************************************************************************/
/*********************************************************************/
/* CE(PD4) CSN(PD5) SCK(PB7) MOSI(PB5) MISO(PB6) IRQ(PD2) */
/*********************************************************************/
#define TX_ADR_WIDTH 5
#define TX_PLOAD_WIDTH 32 //缓冲区大小
#define CE_0 do {PORTD&=0xEF;} while(0)
#define CE_1 do {PORTD|=0x10;} while(0)//PD4
#define CSN_0 do {PORTD&=0XDF;} while(0)
#define CSN_1 do {PORTD|=0X20;} while(0)//PD5
unsigned char TX_ADDRESS[TX_ADR_WIDTH]={0x00,0x00,0x90,0x34,0xA7}; // Define a static TX address
unsigned char rx_buf[TX_PLOAD_WIDTH]; //RX缓冲区
unsigned char tx_buf[TX_PLOAD_WIDTH]; //TX缓冲区
volatile unsigned char flag,date,sta;
void spi_init()
{
DDRB|=0XB0;//SCK、SS and MOSI
DDRB&=~_BV(PB6);//MISO
SPCR = (1 << SPE)|(1 << MSTR)|(1 << SPR0);
SPSR = 0;
}
unsigned char send_spi(unsigned char date)
{
SPSR &= ~(1 << SPIF);
SPDR=date;
while((SPSR&0X80)==0X00);
return SPDR;
}
void interr_0()
{
DDRD&=~_BV(PD2);
MCUCR=0X02;
SREG|=0X80;
GICR=0X40;
}
void init_sys()
{
DDRD|=0x30;
CE_0;
CSN_0;
}
/**************************************************
Function: SPI_RW_Reg();
Description:
Writes value 'value' to register 'reg'
**************************************************/
unsigned char SPI_RW_Reg(BYTE reg, BYTE value)
{
unsigned char a;
CSN_0;
a=send_spi(reg);
send_spi(value); // ..and write value to it..
CSN_1;
return(a); // return nRF24L01 status byte
}
/**************************************************/
/**************************************************/
BYTE SPI_Read(BYTE reg)
{
BYTE reg_val;
CSN_0;//CSN IS LOW
send_spi(reg); // Select register to read from..
reg_val=send_spi(0); // ..then read registervalue
CSN_1;
return(reg_val); // return register value
}
/**************************************************
Function: SPI_Read_Buf();
Description:
Reads 'bytes' #of bytes from register 'reg'
Typically used to read RX payload, Rx/Tx address
**************************************************/
unsigned char SPI_Read_Buf(BYTE reg, BYTE *pBuf, BYTE bytes)
{
unsigned char status,byte_ctr;
CSN_0;//CSN IS LOW
status=send_spi(reg); // Select register to write to and read status byte
for(byte_ctr=0;byte_ctr<bytes;byte_ctr++)
pBuf[byte_ctr] = send_spi(0); // Perform SPI_RW to read byte from nRF24L01
CSN_1;
return(status);
}
/**************************************************/
/**************************************************
Function: SPI_Write_Buf();
Description:
Writes contents of buffer '*pBuf' to nRF24L01
Typically used to write TX payload, Rx/Tx address
**************************************************/
unsigned char SPI_Write_Buf(BYTE reg, BYTE *pBuf, BYTE bytes)
{
unsigned char status,byte_ctr;
CSN_0;//CSN IS LOW
status=send_spi(reg); // Select register to write to and read status byte
for(byte_ctr=0; byte_ctr<bytes; byte_ctr++) // then write all byte in buffer(*pBuf)
send_spi(*pBuf++);
CSN_1;
return(status);
}
/**************************************************/
void init_24l01()
{
SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x0f); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
}
/**************************************************
Function: RX_Mode();
Description:
This function initializes one nRF24L01 device to
RX Mode, set RX address, writes RX payload width,
select RF channel, datarate & LNA HCURR.
After init, CE is toggled high, which means that
this device is now ready to receive a datapacket.
**************************************************/
void RX_Mode(void)
{
CE_0;
SPI_Write_Buf((WRITE_REG + RX_ADDR_P0), TX_ADDRESS, TX_ADR_WIDTH); //Use the same address on the RX device as the TX device
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..
CE_1; // Set CE
}
/**************************************************
Function: TX_Mode();
Description:
This function initializes one nRF24L01 device to
TX mode, set TX address, set RX address for auto.ack,
fill TX payload, select RF channel, datarate & TX pwr.
PWR_UP is set, CRC(2 bytes) is enabled, & PRIM:TX.
ToDo: One high pulse(>10us) on CE will now send this
packet and expext an acknowledgment from the RX device.
**************************************************/
void TX_Mode(void)
{
CE_0;
SPI_Write_Buf((WRITE_REG + TX_ADDR), TX_ADDRESS, TX_ADR_WIDTH); // Writes TX_Address to nRF24L01
SPI_Write_Buf((WRITE_REG + RX_ADDR_P0), TX_ADDRESS, TX_ADR_WIDTH); // RX_Addr0 same as TX_Adr for Auto.Ack
SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // Writes data to TX payload
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_DS enabled..
_delay_ms(5);
CE_1;
}
/**************************************************/
/* 中断函数 */
/**************************************************/
ISR(INT0_vect)
{
flag=1;
sta=SPI_Read(STATUS); // read register STATUS's value
SPI_RW_Reg(WRITE_REG+STATUS,sta);// clear RX_DR or TX_DS or MAX_RT interrupt flag
if(sta&RX_DR) // if receive data ready (RX_DR) interrupt
{
SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH);// read receive payload from RX_FIFO buffer
}
if(sta&MAX_RT)
{
SPI_RW_Reg(FLUSH_TX,0x00);
}
if(sta&TX_DS)
{
;
}
RX_Mode();
}
/********************************************************************
* 文件名 : ATmega32A_NRF24L01
* 描述 : 发送端
*创建人 :69223856@qq.com
* 日期 : 2010/3/10
* 版本号 : V1.0
* 备注 : 时钟频率8.0MHz
***********************************************************************/
#define F_CPU 8000000UL //8M晶振
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include "2401.h"
#define uchar unsigned char
#define uint unsigned int
/**************************************************/
int main()
{
unsigned char i;
init_sys();
spi_init();
interr_0();
init_24l01();
RX_Mode();
PORTA|=0X02;
DDRA&=0XFD;//PA1输入
while(1)
{
if( (PINA&0x02)==0 )//PA1低电平
{
for(i=1;i<4;i++)
{
tx_buf[0]=i;
TX_Mode();
DDRA|=_BV(PA0);
PORTA|=_BV(PA0);
_delay_ms(500);
}
}
}
}
/********************************************************************
* 文件名 : ATmega32A_NRF24L01
* 描述 : 接收端
* 创建人 :69223856@qq.com
* 日期 : 2010/3/10
* 版本号 : V1.0
* 备注 : 时钟频率8.0MHz
***********************************************************************/
#define F_CPU 8000000UL
#include<avr/io.h>
#include<avr/interrupt.h>
#include<util/delay.h>
#include "2401.h"
#include"5110.h"
#define uchar unsigned char
#define uint unsigned int
/**************************************************/
volatile unsigned char i;
void main()
{
DDRA|=0xF1;
DDRB|=0x04;
LCD_init(); //初始化LCD模块
LCD_clear(); //清屏幕
init_sys();
spi_init();
interr_0();
init_24l01();
RX_Mode();
backled1;
while(1)
{
if(flag==1)
{
i=rx_buf[0];
LCD_PutString12x16(16,16,Put_variable(i) );
if(rx_buf[0]==3)
{
PORTA|=0X01;
DDRA|=0X01;
}
else
PORTA&=~_BV(PA0);
flag=0;
}
}
}
/**************************************************/
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