Question

用verilog HDL循环语句来统计8位二进制中含1的数量

Answer 1

hi,

Please see the followings, and do not hesitate to tell me your question,
thanks.

module count_one
(
num1,
num1_vld,

in8,
clk,
rst_n
);

output [3:0] num1; //how many 1 in the signal
outptu num1_vld ; //num1 is valid only when the signal = 1

input [7:0] in8 ;//input 8-digit signal
input clk;
input rst_n;

//apply a count to count 8 periodically
reg [2:0] sht_cnt ;

//3 bit count to count 0~7, so sht_cnt wrap around naturally...
//i.e. sht_cnt will count like this: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2,...
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
sht_cnt <= 3'b0 ;
else
sht_cnt <= sht_cnt + 3'b1 ;
end

//use shift count (sht_cnt) to select which digit you like to check
reg bit_sel ;

always@(*)
begin
case(sht_cnt)
3'h0: bit_sel = in8[0] ;
3'h1: bit_sel = in8[1] ;
3'h2: bit_sel = in8[2] ;
3'h3: bit_sel = in8[3] ;
3'h4: bit_sel = in8[4] ;
3'h5: bit_sel = in8[5] ;
3'h6: bit_sel = in8[6] ;
3'h7: bit_sel = in8[7] ;
default: bit_sel = 1'bx ;//it's only for debug purpose
end

//the signal is used to check when to latch sum of in8 ;
wire num1_vld_p;

assign num1_vld_p = (sft_cnt == 3'h7);

reg [3:0] num1 ;

always@(posedge clk or negedge rst_n)
begin
if(rst_n)
num1 <= 3'b0 ;
else
num1 <= (sft_cnt == 3'h0) ? sel_cnt : (num1 + {2'b0,sel_cnt}) : num1 ;
end

reg num1_vld ;

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
num1_vld <= 1'b0 ;
else
num1_vld <= num1_vld_p ;
end

endmodule

The code is a bit long, so syntax error may occur, please help fix them...^^