Question

在VHDL中IF语句与CASE语句的使用效果有何不同

Answer 1

这两个与C语言很像,
在VHDL里面,一般IF只是用于一个判断,要么是,要么否
case语句一般用来判断优先级的,74138用VHDL编的时候,就是用CASE,
实际上IF的嵌套就是CASE语句，
不知道听明白了没有?（语言表达有限）

Answer 2

They are synthesized to different logic:

"If" will be synthesized to PRIORITY decoding,
"Case" gives you balanced decoding.

Use "Case" when you have complex decoding.
Use "IF" when you need fast critical path.

Example:

if (select = "00") then
out <= A;
elsif (select = "01") then
out <= B;
elsif (select = "10") then
out <= C;
else
out <= D;
end;

This will give you a priority tree that A has smallest delay (1 MUX) while C and D have largest delay (3 MUX)

A ------------------|MUX|---- OUT
B ----------|MUX|---|(3)|
C --|MUX|---|(2)|
D --|(1)|

If you use "CASE" statement the logic is a balanced tree, all signals will have 2 MUX delay.

A --|MUX|
B --|(1)|----|====|
. |MUX3|---- OUT
C --|MUX|----|====|
D --|(2)|