Question

求高手用EDA帮忙做一题~用VHDL语言设计12进制计数器~

用VHDL语言设计12进制计数器，
功能要求：可异步清零，逢12进1，计数到11产生进位信号。
设计要求：编译、仿真、引脚配置、重新编译。

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY UPCOUNTER1_10 IS
PORT(CLK,CLR,EN:IN STD_LOGIC;--时钟输入，异步清零，同步使能;
Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--4位输出;
CO:OUT STD_LOGIC);--高位进位;
END UPCOUNTER1_10;

ARCHITECTURE ART OF UPCOUNTER1_10 IS
SIGNAL X:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,CLR,EN)
BEGIN
IF CLR='1'THEN X<="0000";
else IF clk'event and clk='1' then
IF EN='1'then x<=x+1;
if x<11 then x<=x+1;co<='0';
else x<="0000";co<='1';
end if;
END IF;
END IF;
END IF;
Y<=X;
END PROCESS;
END ART;

考虑到引脚配置，得根据你实际情况来看，我们的试验箱有好几个模式，每个模式对应的引脚配置是不同的。

Answer 2

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity counter_n is
port(data : in std_logic；
load, en, clk, rst,d : in std_logic;
q : out std_logic_vector (3 downto 0));
end counter_n;

architecture behave of counter_n is
signal count : std_logic_vector (3 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
count <= “0000”;
elsif
clk’event and clk = ‘1’ then
if count=“1010”then
count <= 0;
d<=1;
elsif en = '1' then
count <= count + 1;
end if;
end if;
end process;
q <= count;
end behave;

Answer 3

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY UPCOUNTER1_10 IS
PORT(
CLK,CLR,EN:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
CO:OUT STD_LOGIC;
);
END UPCOUNTER1_10;
ARCHITECTURE ART OF UPCOUNTER1_10 IS
BEGIN
PROCESS(CLK,CLR,EN,A)
SIGNAL X:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR='1'THEN
X<="0000";
ELSE IF EN='1'
THEN X<=A;
ELSE IF clk'event and clk='1' then
IF X="1001"THEN
X<="0000";
ELSE X<=X+'1';
END IF;
END IF;
END IF;
END IF;
Y<=X;
END PROCESS;
END ART;

Answer 4

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity count12 is
port(clk:in std_logic;
reset :in std_logic;
co:out std_logic;
output1: out std_logic_vector( 3 downto 0));
end entity;

architecture action of count12 is
begin
process(clk)
variable tmp:integer range 0 to 11;
begin
if(clk'event and clk='1')then
if(tmp<12)then
tmp:=tmp+1;
else
tmp:=0;
end if;
case tmp is
when 0=>output1<="0000";
when 1=>output1<="0001";
when 2=>output1<="0010";
when 3=>output1<="0011";
when 4=>output1<="0100";
when 5=>output1<="0101";
when 6=>output1<="0110";
when 7=>output1<="0111";
when 8=>output1<="1000";
when 9=>output1<="1001";
when 10=>output1<="1010";
when 11=>output1<="1011";
when others=>output1<="0000";
end case;
if(tmp=11)then
co<='1';
else
co<='0';
end if;
if(reset='1')then
output1<="0000";
tmp:=0;
end if;
end if;
end process;
end action;