Question

用VHDL语言设计一个代码转换逻辑电路。把7位的ASCII码转换成7段字符显示代码。

能显示字母A，b，C，d，E，F，H，L，o，P，U，Γ，和一些符号(-，_，=，┫，┣，┓，┏)等。

Answer 1

library ieee;
use ieee.std_logic_1164.all;
entity converse is
port(I_L:in std_logic_vector(0 to 7);
F_L:out std_logic_vector(0 to 7));
end converse;
architecture behave of converse is
begin
case I_L is
when"1000001"=>F_L<="1110111";
when"1100010"=>F_L<="0011111";
when"1000011"=>F_L<="1001110";
when"1100100"=>F_L<="0111101";
when"1000101"=>F_L<="1001111";
when"1000110"=>F_L<="1000111";
when"1001000"=>F_L<="0110111";
when"1001100"=>F_L<="0001110";
when"1101111"=>F_L<="0011101";
when"1010000"=>F_L<="1100111";
when"1010101"=>F_L<="0111110";
when"0000001"=>F_L<="1110000";
when"0101101"=>F_L<="0000001";
when"1011111"=>F_L<="0001000";
when"0111101"=>F_L<="1001000";
when"0000010"=>F_L<="0110001";
when"0000011"=>F_L<="0000111";
when"0000100"=>F_L<="0010001";
when"0000101"=>F_L<="0000101";
when others =>F_L<="XXXXXXX";
end case;
end behave;

Answer 2

大概如此
代码：
library IEEE;
use IEEE.SDT_logic_1164.all;
entity ASCII is
port(
I_L:in std_logic_vector(6 downto 0);
Y: in std_logic_vector(6 downto 0));
end ASCII;
architecture ASCIIp of ASCII is
begin
process(I_L)
begin
case I_L is
when "1000001"=>Y<="1110111";
when "1100010"=>Y<="0111101";
when "1000011"=>Y<="1111000";
when "1100100"=>Y<="0011111";
when "1000101"=>Y<="1111001";
when "1000110"=>Y<="1110001";
when "1001000"=>Y<="0110111";
when "1001111"=>Y<="1100011";
when "1001100"=>Y<="0111000";
when "1010000"=>Y<="1110011";
when "1010101"=>Y<="0111110";
when "0000010"=>Y<="1110010";
when "0111101"=>Y<="0001001";
when "0010100"=>Y<="0000111";
when "0000011"=>Y<="0110001";
when "0011111"=>Y<="0000101";
when "0011010"=>Y<="0010001";
when others =>Y<="XXXXXXX";
end case;
end process;
end ASCIIp;

Answer 3

没逻辑图吗~~~

Answer 4

没人会做啊，盛老师的题目！！！！！！我悬赏200分都没人做！！！！