Question

异步FIFO用Verilog编写，用Quratus2验证，程序已经写好了，测试代码怎么写呀？

// 写指针与"满"逻辑
module wptr_full(wfull, wptr, afull_n, wreq, wclk, wrst_n);
parameter ADDR_WIDTH = 4;
output wfull;
output [ADDR_WIDTH-1:0] wptr;
input afull_n;
input wreq,wclk,wrst_n;
reg [ADDR_WIDTH-1:0] wptr,wbin;
reg wfull, wfull2;
wire [ADDR_WIDTH-1:0] wgnext,wbnext;

//GRAYSTYLE pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) begin
wbin <= 0;
wptr <= 0;
end
else begin
wbin <= wbnext;
wptr <= wgnext;
end

//increment the binary count if not full
assign wbnext = !wfull ? wbin + wreq : wbin;
assign wgnext = (wbnext>>1) ^ wbnext; //binary-to-gray conversion

always @(posedge wclk or negedge wrst_n or negedge afull_n)
if (!wrst_n)
{wfull,wfull2} <= 2'b00;
else if (!afull_n)
{wfull,wfull2} <= 2'b11;
else
{wfull,wfull2} = {wfull2,~afull_n};
endmodule

// 读指针与"空"逻辑
module rptr_empty(rempty,rptr,aempty_n,rreq,rclk,rrst_n);
parameter ADDR_WIDTH = 4;
output rempty;
output [ADDR_WIDTH-1:0] rptr;
input aempty_n;
input rreq,rclk,rrst_n;
reg [ADDR_WIDTH-1:0] rptr, rbin;
reg rempty, rempty2;
wire [ADDR_WIDTH-1:0] rgnext,rbnext;

//GRAYSTYLE pointer
always@(posedge rclk or negedge rrst_n)
if (!rrst_n)begin
rbin<=0;
rptr<=0;
end
else begin
rbin<=rbnext;
rptr<=rgnext;
end
//increment the binary count if not full
assign rbnext=!rempty?rbin+rreq:rbin;
assign rgnext =(rbnext>>1)^rbnext;//binary—to—gray conversion
always@(posedge rclk or negedge rrst_n or negedge aempty_n)
if(!aempty_n){rempty,rempty2}<=2`b11;
else {rempty,rempty2}<={rempty2,~aempty_n};
endmodule

// 异步比较器
module async_cmp(aempty_n,afull_n,wptr,rptr,wrst_n);
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
output aempty_n,afull_n;
input [N:0] wptr,rptr;
input wrst_n;
reg direction;
wire high = 1'b1;
wire dirset_n = ~( (wptr[N]^rptr[N-1]) & ~(wptr[N-1]^rptr[N]));
wire dirclr_n = ~((~(wptr[N]^rptr[N-1])&(wptr[N-1]^rptr[N]))|~wrst_n);

always @(posedge high or negedge dirset_n or negedge dirclr_n)
if (!dirclr_n) direction = 1'b0;
else if (!dirset_n) direction = 1'b1;
else direction = high;

assign aempty_n = ~((wptr == rptr) && !direction); // "接近空"标志
assign afull_n = ~((wptr == rptr) && direction); // "接近满"标志
endmodule 这是程序

Answer 1

写一个testbench就好了，fifo的比较好写
上网随便搜个tb的例子，改改就可以了
建议你写渐加数，写满然后读
还有就是写渐加数，不空就读

Answer 2

VERILOG HDL 应用程序设计 实例精讲 上的例子
居然说是写的