Question

VHDL代码解释

entity bcfetch is
generic ( 类属
jpc_width : integer:=12; -- address bits of java byte code pc
pc_width : integer:=11 -- address bits of internal instruction rom
);
port (
clk, reset : in std_logic;

jpc_out : out std_logic_vector(jpc_width downto 0); -- jpc read
din : in std_logic_vector(31 downto 0); -- A from stack
jpc_wr : in std_logic;

-- connection to mmu

jfetch : in std_logic;
jopdfetch : in std_logic;

zf, nf : in std_logic;
eq, lt : in std_logic;

jbr : in std_logic;

jpaddr : out std_logic_vector(pc_width-1 downto 0); -- address for JVM
opd : out std_logic_vector(15 downto 0) -- operands
);
end bcfetch;

architecture rtl of bcfetch is

--
-- jtbl component (generated vhdl file from Jopa!)
--
-- logic rom (unregistered)
--
component jtbl is
port (
bcode : in std_logic_vector(7 downto 0);

q : out std_logic_vector(pc_width-1 downto 0)
);
end component;

--
-- jbc component (use technology specific vhdl-file cyc_jbc,...)
--
-- ajbc,xjbc are OLD!
-- check if ajbc.vhd can still be used (multicycle write!)
--
-- dual port ram
-- wraddr and wrena registered
-- rdaddr is registered
-- indata registered
-- outdata is unregistered
--
component jbc
PORT
(
address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

signal jbc_addr : std_logic_vector(jpc_width-1 downto 0);
signal jbc_data : std_logic_vector(7 downto 0);

signal jbc_mux : std_logic_vector(jpc_width downto 0);
signal jbc_q : std_logic_vector(7 downto 0);

signal jpc : std_logic_vector(jpc_width downto 0);
signal jpc_br : std_logic_vector(jpc_width downto 0);
signal jmp_addr : std_logic_vector(jpc_width downto 0);

signal jinstr : std_logic_vector(7 downto 0);
signal tp : std_logic_vector(3 downto 0);
signal jmp : std_logic;

signal jopd : std_logic_vector(15 downto 0);

--
-- signals for interrupt handling
--

signal bytecode : std_logic_vector(7 downto 0);

-- synthesis translate_off
-- synthesis translate_on

--
-- signals for method cache (jbc)
--
begin

--
-- interrupt processing at bytecode fetch level
--

--
-- TODO: exception and int in the same cycle: int gets lost
--
--
-- bytecode mux on interrupt
-- jpc is one too high after generating int_taken
-- this is corrected in jvm.asm
--

--
-- java byte code fetch and branch
-- interrupt and exception mux are in jtbl
--

bytecode <= jbc_q; -- register this for an additional pipeline stage

jt: jtbl port map(bytecode, jpaddr);

jbc_addr <= jbc_mux(jpc_width-1 downto 0);
jbc_q <= jbc_data;

Answer 1

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;加入这个让你可以使用加减运算，其他的就不用解释了
use ieee.std_logic_unsigned.all;

entity mul is

generic (
width : integer := 32 -- one data word
);定义width为integer且等于32

port (
clk : in std_logic;时钟输入

ain : in std_logic_vector(width-1 downto 0);A口32位输入
bin : in std_logic_vector(width-1 downto 0);B口32位输入
wr : in std_logic; -- write starts multiplier；控制位
dout : out std_logic_vector(width-1 downto 0)；DATAOUT32位输出
);
end mul;
；以上为引脚定义

architecture rtl of mul is
--
-- Signals
--
signal count : integer range 0 to width/2;定义整形信号COUNT
signal p : unsigned(width-1 downto 0);定义非符号信号P
signal a, b : unsigned(width-1 downto 0);定义非符号A，B

begin

process(clk)；时钟变化时运行以下程序

variable prod : unsigned(width-1 downto 0);定义PROD变量

begin
if rising_edge(clk) then；时钟上升沿
if wr='1' then；如果WR输入1
p <= (others => '0');P清零
a <= unsigned(ain);AIN放入A
b <= unsigned(bin);BIN放入B
else；如果WR输入0

prod := p;PROD得到P的值
if b(0) = '1' then;如果B（0）=1
prod := prod + a;PROD=PROD+A
end if;
if b(1) = '1' then；如果B（1）=1
prod := (prod(width-1 downto 1) + a(width-2 downto 0)) & prod(0);；A前31位赋值给PROD前31位，然后PROD（0）不变
end if;
p <= prod;P=PROD

a <= a(width-3 downto 0) & "00";A左移两位，后面补0，即A=A*4
b <= "00" & b(width-1 downto 2);B右移两位，前面补0,即B=B/4

end if;
end if;
end process;

dout <= std_logic_vector(p);把P转换为 std_logic_vector然后输出到DATAOUT

end rtl;
；以上为结构定义

Answer 2