Question

用verilog怎么写16-4编码啊 新手求教

Answer 1

module code16_4(in,out);
input [15:0] in;
output [3:0] out;

assign out=
(in[0]==1)?4'd0:
(in[1]==1)?4'd1:
(in[2]==1)?4'd2:
(in[3]==1)?4'd3:
(in[4]==1)?4'd4:
(in[5]==1)?4'd5:
(in[6]==1)?4'd6:
(in[7]==1)?4'd7:
(in[8]==1)?4'd8:
(in[9]==1)?4'd9:
(in[10]==1)?4'd10:
(in[11]==1)?4'd11:
(in[12]==1)?4'd12:
(in[13]==1)?4'd13:
(in[14]==1)?4'd14:
(in[15]==1)?4'd15:4'bx;
endmodule