Question

VHDL编译出现如下的问题怎么解决

Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "sound" is stuck at GND
Warning (13410): Pin "q[2]" is stuck at GND
Warning (13410): Pin "q[1]" is stuck at GND
还有Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin sound has GND driving its datain port
Info: Pin q[2] has GND driving its datain port
Info: Pin q[1] has GND driving its datain port

Answer 1

Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "sound" is stuck at GND
Warning (13410): Pin "q[2]" is stuck at GND
Warning (13410): Pin "q[1]" is stuck at GND
这个的意思是您的这几个输出管脚直接接地了（意思是它们的值一直都是0）。当然如果这符合您的设计要求这种警告可以不管。
Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin sound has GND driving its datain port
Info: Pin q[2] has GND driving its datain port
Info: Pin q[1] has GND driving its datain port
这几句的意思是您没有对这三个信号进行驱动。

Answer 2

问题应该出在寄存器register的写法上，具体是这段
when s10=>
red<="1111111111";
if a'event and a='1' then
next_s<=s0;
else
next_s<=s10;
end if;
if a'event and a='1'和if rising_edge(a)是等同的，这实际上是写了一个寄存器，由时钟上升沿触发，a在这里实际就是作为clock。
需要理解的是这是寄存器，而不是简单的if条件语句。这段语句会使next_s<=s10成为长期的状态，而只在时钟a的上升沿短暂变为s0，这个信号的赋值要在瞬间变为s0，再变回s10，有点类似一个冲激信号了。实际的电路是无法实现的，所以couldn't implement。
正确的寄存器写法不应该对时钟信号有else，而应用其他逻辑信号控制条件，如
if a'event and a='1' then
if b='1' then
next_s<=s0;
else
next_s<=s1;
end if;
end if;

写vhdl和verilog经常是单写一个模块没事，连到一起就出问题了，总结下来还是本身单个模块写的不够严谨。