Question

用VHDL编程时总是出现这样的错误

Error (10821): HDL error at test.vhd(125): can't infer register for "count3[0]" because its behavior does not match any supported register model
Error (10821): HDL error at test.vhd(125): can't infer register for "count3[1]" because its behavior does not match any supported register model
Error (10821): HDL error at test.vhd(125): can't infer register for "count3[2]" because its behavior does not match any supported register model
Error (10821): HDL error at test.vhd(125): can't infer register for "count3[3]" because its behavior does not match any supported register model
Error (10821): HDL error at test.vhd(125): can't infer register for "count3[4]" because its behavior does not match any supported register model
Error (10822): HDL error at test.vhd(116): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at test.vhd(125): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
求高手解答一下。
程序是这样的：
process(en,clk1)
begin

if en='1' then
if clk1'event and clk1='1' then
if count3=19 then
count3<=0;
else count3<=count3+1;
end if;
end if;
end if;

if en='0' then
if key2'event and key2='1' then
if a<9 then
a<=count3+1;
end if;
end if;
end if;
end process;

Answer 1

以上是属于多时钟问题！在设计时往往会遇到这种情况，需要对外部某个输入信号进行判断，当其出现上跳或下跳沿时，执行相应的操作，而该信号不像正常时钟那样具有固定占空比和周期，而是很随机，需要程序设计判断其上跳沿出现与否。就会写出如上程序！
解决的办法可以如下，将clk1和key2 增加一级状态
lcx 寄存，通过对 clk1或key2 和lcx状态判断上跳与否，改正程序如下：
signal lcx:std_logic;
signal a,count3:integer;
begin
process(en,clk)
begin
if en='1' then
if clk'event and clk='1' then
lcx<=clk1;
if lcx='0' and clk1='1' then
if count3=19 then
count3<=0;
else count3<=count3+1;
end if;
end if;
end if;
end if;

if en='0' then
if clk'event and clk='1' then
lcx<=key2;
if lcx='0' and key2='1' then
if a<9 then
a<=count3+1;
end if;
end if;
end if;
end if;
end process;

Answer 2

你的上面的警告分两类，第一类是CNT3的，第二类是 对if clk1'event and clk1='1' then
if key2'event and key2='1' then的 先说第二个， 一般一个进程里面 不能对两个时钟信号进行判断，操作，去百度文库里面找找有相关解决方法，第一个应该说的是cnt3定义类型有问题吧，我不太明白

Answer 3

if 语句是顺序语句，必须在进程中使用
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux IS
PORT(a,b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
c:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); --错误1
end mux;

ARCHITECTURE example OF mux IS
begin
process（a，b，sel）--if 语句是顺序结构语句，必须在进程中使用
begin
if (sel="00") then
c<="00000000";
elsif (sel="01"）then
c<=a;
elsif (sel="10") then
c<=b;
else
c<=（others=>Z）;
end if;
end process;
end example;

Answer 4

很同意第一个答案，说的很好，学习学习