Question

我现在有一个Quartus II的程序，编译没有报错，但是无法仿真，求高手指点哪里错了？

彩灯控制器
要求：
1．有八只LED，L0……L7
2．显示顺序如下表
3．显示间隔为0.25S，0.5S，1S，2S可调。

序号 L0 L1 L2 L3 L4 L5 L6 L7
0 1 1 1 1 1 1 1 0
1 0 1 1 1 1 1 1 1
2 1 0 1 1 1 1 1 1
3 1 1 0 1 1 1 1 1
4 1 1 1 0 1 1 1 1
5 1 1 1 1 0 1 1 1
6 1 1 1 1 1 0 1 1
7 1 1 1 1 1 1 0 1
8 1 1 1 1 1 1 1 0
9 1 1 1 1 1 1 1 1
10 0 1 1 1 1 1 1 1
11 0 0 1 1 1 1 1 1
12 0 0 0 1 1 1 1 1
13 0 0 0 0 1 1 1 1
14 0 0 0 0 0 1 1 1
15 0 0 0 0 0 0 1 1
16 0 0 0 0 0 0 0 1
17 0 0 0 0 0 0 0 0
18 1 0 0 0 0 0 0 0
19 1 1 0 0 0 0 0 0
20 1 1 1 0 0 0 0 0
21 1 1 1 1 0 0 0 0
22 1 1 1 1 1 0 0 0
23 1 1 1 1 1 1 0 0
24 1 1 1 1 1 1 1 0
25 1 0 0 0 0 0 0 0
26 0 1 0 0 0 0 0 0
27 0 0 1 0 0 0 0 0
28 0 0 0 1 0 0 0 0
29 0 0 0 0 1 0 0 0
30 0 0 0 0 0 1 0 0
31 0 0 0 0 0 0 1 0
32 0 0 0 0 0 0 0 1
（分频器、驱动器，可以使用状态机转换做）
module ledctrl (clk,ctrl,l);
input clk;
input[1:0] ctrl;

output [7:0] l;

reg [7:0] counter,ctrlcounter,l;

reg[5:0] sreg;

always //timer control
begin
case (ctrl)
2'b00: ctrlcounter = 8'd31;
2'b01: ctrlcounter = 8'd63;
2'b10: ctrlcounter = 8'd127;
2'b11: ctrlcounter = 8'd255;
default : ctrlcounter = 8'd255;
endcase
end

always @(posedge clk) //clock counter
begin
counter = counter + 8'd1;
if (counter == ctrlcounter)
begin
sreg = sreg + 6'd1;
counter = 8'd0;
end
if (sreg == 6'd33)
sreg = 6'd0;
end

always
begin
case ( sreg )
6'd0: l <= 8'b1111_1110;
6'd1: l <= 8'b0111_1111;
6'd2: l <= 8'b1011_1111;
6'd3: l <= 8'b1101_1111;
6'd4: l <= 8'b1110_1111;
6'd5: l <= 8'b1111_0111;
6'd6: l <= 8'b1111_1011;
6'd7: l <= 8'b1111_1101;
6'd8: l <= 8'b1111_1110;
6'd9: l <= 8'b1111_1111;
6'd10: l <= 8'b0111_1111;
6'd11: l <= 8'b0011_1111;
6'd12: l <= 8'b0001_1111;
6'd13: l <= 8'b0000_1111;
6'd14: l <= 8'b0000_0111;
6'd15: l <= 8'b0000_0011;
6'd16: l <= 8'b0000_0001;
6'd17: l <= 8'b0000_0000;
6'd18: l <= 8'b1000_0000;
6'd19: l <= 8'b1100_0000;
6'd20: l <= 8'b1110_0000;
6'd21: l <= 8'b1111_0000;
6'd22: l <= 8'b1111_1000;
6'd23: l <= 8'b1111_1100;
6'd24: l <= 8'b1111_1110;
6'd25: l <= 8'b1000_0000;
6'd26: l <= 8'b0100_0000;
6'd27: l <= 8'b0010_0000;
6'd28: l <= 8'b0001_0000;
6'd29: l <= 8'b0000_1000;
6'd30: l <= 8'b0000_0100;
6'd31: l <= 8'b0000_0010;
6'd32: l <= 8'b0000_0001;

default: l <= 8'b1111_1110;
endcase
end
endmodule

Answer 1

always 后没有接敏感列表, 仿真时没有触发动作, 结果值无法传递(敏感列表对综合只起到判别逻辑的时序和组合的区别,但是对于仿真是必须的)。应该就是这个原因，你被敏感列表加上看一下！

还有，你的阻塞赋值和非阻塞赋值错了，你看一下， always @(posedge clk) 里用 “<=”
always @(*) 后用 “=”，你好像用的不对啊！

Answer 2

是不是忘记加时序约束了呢？如果时钟速率比较高，必须加时序约束。

追问

时序约束没必要吧？我仿真的结果一直是卡在default: l <= 8'b1111_1110;这里的，也就是说似乎没开始计数，直接进入default，能帮我找找毛病么？