Question

您好 我现在急需一个verilog写的自适应FIR滤波器的程序 您能帮我一下不

Answer 1

module INV_FIR(clk,x_in,y);
input clk;
input [7:0] x_in;
output [10:0] y;

reg [18:0] m0,m1,m2,m3,m4,m5;//used for piple
reg [18:0] x40,x61,x70; //modulus of filter
reg [18:0] x32,x64,x8,x2; //medians which filter will use
reg [7:0] x;
wire [18:0] x_ext;

assign x_ext={{9*{x[7]}},x};// extend x
assign y=(m0>8); // output

always @ (posedge clk)
begin
x<=x_in;

m0<=m1+x40;
m1<=m2+x61;
m2<=m3+x70;
m3<=m4+x61;
m4<=x40;
end

always @ (posedge clk) //this modulus will multi with x
begin
x40<=x32+x8;
x61<=x64-x2-x;
x70<=x64+x8-x2;
end
always @ (x_ext) //some medians which will be used for multiplication
begin
x2<=(x_ext<<1);
x8<=(x2<<2);
x32<=(x8<<2);
x64<=(x32<<1);
end
endmodule
这是个以前做的fir 给你参考一下吧。