Question

求大神帮忙，VHDL语言，设计一个数字信号发生器，谢啦

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sequence_generator IS
PORT(clock: IN std_logic;
reset: IN std_logic;
Q: OUT std_logic_vector(7 DOWNTO 0));
END sequence_generator;
ARCHITECTURE behavioral OF sequence_generator IS
SIGNAL Qt: std_logic_vector(7 DOWNTO 0);
BEGIN
PROCESS(reset,clock)
variable temp: std_logic;
BEGIN
IF reset='0' THEN
Qt <= "00000101";
ELSIF rising_edge(clock) THEN
temp := Qt(7);
Qt(7 DOWNTO 1) <= Qt(6 DOWNTO 0);
Qt(0) <= temp;
END IF;
END PROCESS;
Q <= Qt;
END behavioral;