Question

如何用VHDL语言编写60进制减法计数器

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY jiancounter IS

PORT
(
SI : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
FI : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
EN : IN STD_LOGIC;
LDN : IN STD_LOGIC;
SO : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
FO : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
RCO : OUT STD_LOGIC
);

END jiancounter;

ARCHITECTURE a OF jiancounter IS

SIGNAL S : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL F : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL C : STD_LOGIC;

BEGIN

PROCESS (CLK)

BEGIN

IF CLR = '0' THEN

S<= "0000";
F<= "0000";
C<= '0';

ELSIF (CLK'EVENT AND CLK= '1') THEN

IF LDN = '0' THEN

S<= SI;
F<= FI;
C<='0';

ELSE

IF EN = '0' THEN

S <=S;
F <=F;
C <='0';

ELSE

IF (S="0000" AND F="0000") THEN

S <="1001";
F <="0101";
C <='1';

ELSE

IF S ="0000" THEN

S <="1001";
CASE F IS
WHEN "0001"=>F<="0000";
WHEN "0010"=>F<="0001";
WHEN "0011"=>F<="0010";
WHEN "0100"=>F<="0011";
WHEN "0101"=>F<="0100";
WHEN OTHERS => NULL;
END CASE;
ELSE
CASE S IS
WHEN "0000"=>S<="1001";
WHEN "0001"=>S<="0000";
WHEN "0010"=>S<="0001";
WHEN "0011"=>S<="0010";
WHEN "0100"=>S<="0011";
WHEN "0101"=>S<="0100";
WHEN "0110"=>S<="0101";
WHEN "0111"=>S<="0110";
WHEN "1000"=>S<="0111";
WHEN "1001"=>S<="1000";
WHEN OTHERS => NULL;
END CASE;
F <= F;

END IF;
C <='0';
END IF;

END IF;

END IF;

END IF;
SO<=S;
FO<=F;
RCO<=C;
END PROCESS;

END a;
这是我编的程序，但在两段case语句行内出现了15个错误，哪位高手帮忙解决一下？

Answer 1

你最好把各端口的用处说明一下。

主要的问题是：你的F定义为 STD_LOGIC_VECTOR(5 DOWNTO 0)
可在使用差罩戚中只虚陵给出了4位的数据。

好好闷判再考虑考虑