Question

我用modelsim编译的时候出现下面的错误，不知道怎么改，请各位会的高手帮忙看一下

** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(61): (vcom-1089) Only one discrete range allowed in slice name of "std_logic_2d".
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(61): (vcom-1136) Unknown identifier "std_logic_2d".
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(95): (vcom-1141) Identifier "lpm_mux" does not identify a component declaration.
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(110): VHDL Compiler exiting
出错的程序是lpm_mux_component : lpm_mux和SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 11 DOWNTO 0);这两行，该怎么改啊

Answer 1

STD_LOGIC_2D (1 DOWNTO 0, 11 DOWNTO 0);
这个是？？？
2维数组不是这样用的

TYEP row_type IS ARRAY(11 DOWNTO 0) OF STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL sub_wire4 : row_type ;

Answer 2

std_logic_2d 改成 std_logic_vector