Question

jlink commander不能用，请教是什么原因？

Answer 1

There are several reasons why the CPU core can not be halted.
Either the memory wait signal of the core is still enabled or CPU disables the clock (wrong PLL clock settings/CPU enters power-save mode).
Therefore the core cannot communicate via JTAG.
The only way to gain control of the core via JTAG is to reset it and halt it immediately.
BTW: Which STR7xx are you using?
Could you please do the following:
Start the J-Link commander (JLink.exe)
Set a very high JTAG-speed by typing "speed [speed in kHz], for example "speed 8000" and press enter. If you are using a STR75x core - a TDMI-S core, this may not work.
Now type "rx 0" - This will reset the core as quickly as possible. The higher the speed the earlier the core is stopped.
You should see:
Reset delay: 0 ms
Reset type NORMAL: Using RESET pin, halting CPU after Reset
Info: Resetting target using RESET pin
The core is halted after reset. Type "regs" to see the CPU registers:
PC: (R15) = 00000000, CPSR = 000000D3 (SVC mode, ARM FIQ dis. IRQ dis.)
R0 = A0000054, R1 = 00008040, R2 = 00000000, R3 = 20000004
R4 = 000000E1, R5 = 000000C7, R6 = 0000004D, R7 = 000000BD
USR: R8 =00000000, R9 =00000000, R10=00000001, R11 =00000001, R12 =00000099
R13=200007FC, R14=000000C7
FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11 =00000000, R12 =00000000
R13=04000000, R14=00000000, SPSR=C00000FF
SVC: R13=00000000, R14=000000F4, SPSR=000000FF
ABT: R13=00000000, R14=00000000, SPSR=D000005F
IRQ: R13=20000900, R14=00000000, SPSR=F00000F7
UND: R13=00000000, R14=00000000, SPSR=D000007A
If you can see the registers' contents, the next step will be to erase the contents of the flash. Use J-Flash and set the following settings:
JTAG\JTAG speed before/after init to 8000kHz (or the value you tried with J-Link commander)
CPU\Init sequence: Action type: Reset, Type: 0, Delay: 0ms
Now connect to the target and select "Erase chip" to erase the flash contents.

Answer 2