Question

求VHDL高手：难道是if里面不能加例化语句？ 为什么把port map 那句去了就能执行，加上后就出错

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder is
port( x,y,cin:in std_logic;
co,s:out std_logic);
end adder;

architecture a_adder of adder is
signal w:std_logic_vector(2 downto 0);
begin
w<=x & y & cin;
process(w)
begin
case w is
when "000"=>co<='0';s<='0';
when "001"=>co<='0';s<='1';
when "010"=>co<='0';s<='1';
when "011"=>co<='1';s<='0';
when "100"=>co<='0';s<='1';
when "101"=>co<='1';s<='0';
when "110"=>co<='1';s<='0';
when others=>co<='1';s<='1';
end case;
end process;
end a_adder;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder_8 is
port( m,n:in std_logic_vector(7 downto 0);
cout:out std_logic;
sout:buffer std_logic_vector(7 downto 0));
end adder_8;

architecture add of adder_8 is

component adder
port( x,y,cin:in std_logic;
co,s:out std_logic);
end component;

signal tmp0:std_logic_vector(7 downto 0);
begin
u0:adder
port map(m(0),n(0),'0',tmp0(0),sout(0));
generate_1:for i in 0 to 6 generate
u1_7: adder port map(m(i+1),n(i+1),tmp0(i),tmp0(i+1),sout(i+1));
end generate;
cout<=tmp0(7);
end add;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mul_8 is
port( a,b:in std_logic_vector(7 downto 0);
s_out:out std_logic_vector(15 downto 0));
end mul_8;

architecture a_mul of mul_8 is

component adder_8
port( m,n:in std_logic_vector(7 downto 0);
cout:out std_logic;
sout:buffer std_logic_vector(7 downto 0));
end component;

signal c: std_logic_vector(7 downto 0);
signal d:std_logic_vector(15 downto 0);
signal tmp:std_logic;
begin
process(a,b)
begin
tmp<='0';
if(b(0)='0') then c:=(others=>'0');
else c<=a;
end if;
xx:for i in 0 to 6 loop
d(i)<=c(i);
c<=tmp & c(7) & c(6) & c(5) & c(4) & c(3) & c(2) & c(1);
if(b(i+1)='1') then
u:adder_8
port map(a,c,tmp,c);
else tmp<='0';
end if;
end loop xx;
s_out <= tmp & c & d(6) & d(5) & d(4) & d(3) & d(2) & d(1) & d(0);
end process;
end a_mul;

Answer 1

。。。。。。。。。。。。。。。
模块例化是并行语句，你放入process中肯定错了。。process 中的所有语句都是顺序执行的。。