Question

这是一个用vhdl语言写的60进制计数器，有错误，请高手指点错误在哪儿

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt60_second is
port(clk,clr,en:in std_logic;
s1,s0:out std_logic_vector(3 downto 0);
co:out std_logic);
end cnt60_second;
architecture one of cnt60_second IS
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clr='0'
then cnt1:="0000";cnt0:="0000";
else if (clk'event and clk='1')then
if cnt0<"1001" then
cnt0:=cnt0+1;co<='0';
else if cnt1<5 then
cnt1:=cnt1+1;cnt0:=(others=>'0');
else if cnt0="1001" and cnt1="0101" then
co<=1;cnt1:="0000";cnt0:="0000";
else co<=0;
end if;
end if;
end if;
end if;
end if;
s1<=cnt1;
s0<=cnt2;
end process;
end one;

Error (10517): VHDL type mismatch error at cnt60_second.vhd(23): std_logic type does not match integer literal

Answer 1

错误很明显 根据你定义的co输出数据类型 凡是给co赋值的地方应该用co<='1';注意单引号

Answer 2

一个进程里不能有两个时钟驱动！