Question

请问如何用verilog写8个流水灯

Answer 1

module LED_Module(Clock,LED_Data_Port);

input Clock;
output LED_Data_Port;

reg [7:0] LED_Data_Port; //LED数据口
reg [3:0] led_d; //LED显示数据
//================================================
integer cnt_led;
//==================================================
always @(posedge Clock)
begin
cnt_led <=cnt_led + 1;
if(cnt_led == 20000000)
begin
cnt_led <= 0;
led_d <= led_d + 1;
if(led_d == 8)
led_d <= 0;
end
end
always @( led_d ) begin
case (led_d)
4'd1:
LED_Data_Port[7:0] <= 8'b1000_0000;//8'b1000_0001;
4'd2:
LED_Data_Port[7:0] <= 8'b0000_0001;//8'b1100_0011;
4'd3:
LED_Data_Port[7:0] <= 8'b0000_0010;//8'b1110_0111;
4'd4:
LED_Data_Port[7:0] <= 8'b0000_0100;//8'b1111_1111;
4'd5:
LED_Data_Port[7:0] <= 8'b0000_1000;//8'b0001_1000;
4'd6:
LED_Data_Port[7:0] <= 8'b0001_0000;//8'b0011_1100;
4'd7:
LED_Data_Port[7:0] <= 8'b0010_0000;//8'b0111_1110;
4'd8:
LED_Data_Port[7:0] <= 8'b0100_0000;//8'b1111_1111;
default:
LED_Data_Port[7:0] <= 8'b0000_0000;//8'b1111_1111;
endcase
end

endmodule

追问

always @(posedge Clock)
begin
cnt_led <=cnt_led + 1;
if(cnt_led == 20000000)
begin
cnt_led <= 0;
led_d <= led_d + 1;
if(led_d == 8)
led_d <= 0;
end
end
这个是分频器吧，好像有点问题。

追答

我实际运行过可以实现，请问有什么问题呢？

Answer 2

这个，设定一个模块，输出就是流水端口，按一定时间，循环右移或者左移就能达到目的