Question

VHDL序列信号发生器问题

编好的程序如下：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MY_100110 IS
PORT(
CLK:INSTD_LOGIC;
Z :OUTSTD_LOGIC
);
END MY_100110;

ARCHITECTURE RTL OF MY_100110 IS

TYPE STATE_TYPE IS(S0,S1,S2,S3,S4,S5);
SIGNAL CURRENT_STATE,NEXT_STATE:STATE_TYPE;
BEGIN
SYNCH: PRECESS
BEGIN
WAIT UNTIL CLK'EVENT AND CLK='1';
CURRENT_STATE<=NEXT_STATE;
END PROCESS;

STATE_TRANS:PROCESS(CURRENT_STATE)
BEGIN
CASE CURRENT_STATE IS
WHEN S0=>
NEXT_STATE<=S1;
Z<='1';
WHEN S1=>
NEXT_STATE<=S2;
Z<='0';
WHEN S2=>
NEXT_STATE<=S3;
Z<='0';
WHEN S3=>
NEXT_STATE<=S4;
Z<='1';
WHEN S4=>
NEXT_STATE<=S5;
Z<='1';
WHEN S5=>
NEXT_STATE<=S0;
Z<='0';
END CASE;

END PROCESS;

END RTL;

用quartusⅡ运行有5个错误，限于水平有限，求大神帮助修改！

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MY_100110 IS
PORT(
CLK:IN STD_LOGIC;
Z :OUT STD_LOGIC
);
END MY_100110 ;

ARCHITECTURE RTL OF MY_100110 IS

TYPE STATE_TYPE IS(S0,S1,S2,S3,S4,S5);
SIGNAL CURRENT_STATE,NEXT_STATE:STATE_TYPE;
BEGIN
SYNCH: PROCESS
BEGIN
WAIT UNTIL CLK'EVENT AND CLK='1';
CURRENT_STATE<=NEXT_STATE;
END PROCESS;

STATE_TRANS:PROCESS(CURRENT_STATE)
BEGIN
CASE CURRENT_STATE IS
WHEN S0=>
NEXT_STATE<=S1;
Z<='1';
WHEN S1=>
NEXT_STATE<=S2;
Z<='0';
WHEN S2=>
NEXT_STATE<=S3;
Z<='0';
WHEN S3=>
NEXT_STATE<=S4;
Z<='1';
WHEN S4=>
NEXT_STATE<=S5;
Z<='1';
WHEN S5=>
NEXT_STATE<=S0;
Z<='0';
END CASE;

END PROCESS;

END RTL;