Question

quartus ii&vhdl程序运行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bit_rtl_reg_clk is
port(pin:bit_vector;
cntl:bit_vector;
pout:out bit_vector;
clk:bit);
end bit_rtl_reg_clk;
architecture func of bit_rtl_reg_clk is
begin
process
begin
wait until clk'EVENT and clk='1';
if (cnt1='1')then pout<=pin;
end if;
end process;
end func;
为什么运行总是提示
Error (10482): VHDL error at func.vhd(15): object "cnt1" is used but not declared
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 3 warnings
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 3 warnings

Answer 1

你在端口声明中明明声明了“cntl”，但是在结构体中却引用“cnt1”，当然VHDL不认得了！