Question

在PROTEL 99 SE中自动步线以后，进行DRC检查出现如下错误是什么原因：Rule Violations :2

Protel Design System Design Rule Check
PCB File : Documents\try.PCB
Date : 11-Aug-2007
Time : 14:20:54

Processing Rule : Width Constraint (Min=20mil) (Max=20mil) (Prefered=20mil) (Is on net VCC )
Rule Violations :0

Processing Rule : Width Constraint (Min=20mil) (Max=20mil) (Prefered=20mil) (Is on net GND )
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Violation Pad Y2-0(45670mil,47550mil) MultiLayer Actual Hole Size = 154.166mil
Violation Pad Y1-0(42470mil,46270mil) MultiLayer Actual Hole Size = 154.166mil
Rule Violations :2

Processing Rule : Width Constraint (Min=10mil) (Max=20mil) (Prefered=20mil) (On the board )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )
Violation between Pad R22-2(43860mil,49960mil) MultiLayer and
Track (41380mil,50000mil)(45620mil,50000mil) KeepOutLayer
Rule Violations :1

Processing Rule : Broken-Net Constraint ( (On the board ) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0

Violations Detected : 3
Time Elapsed

Answer 1

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Violation Pad Y2-0(45670mil,47550mil) MultiLayer Actual Hole Size = 154.166mil
Violation Pad Y1-0(42470mil,46270mil) MultiLayer Actual Hole Size = 154.166mil
Rule Violations :2
这里是孔的大小有问题~你设置的是最小1MIL最大100MIL可实际上是154.166~
你可以到设计规则里改~也可以在板子上把你的孔改成设计规则范围内的Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )
Violation between Pad R22-2(43860mil,49960mil) MultiLayer and
Track (41380mil,50000mil)(45620mil,50000mil) KeepOutLayer
Rule Violations :1
这里是焊盘和线段离的太近了~