Question

quartus ii 仿真通过 但没波形，怎么回事？程序实现测频功能

控制器程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY kz IS
PORT(CLK: IN STD_LOGIC;
TSIEN: OUT STD_LOGIC;
CLR_CNT:OUT STD_LOGIC;
LOAD: OUT STD_LOGIC );
END kz;
ARCHITECTURE BEHAV OF kz IS
SIGNAL Div2CLK:STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
Div2CLK<=NOT Div2CLK;
END IF;
END PROCESS;
PROCESS(CLK,Div2CLK)
BEGIN
IF CLK='0'AND Div2CLK='0' THEN
CLR_CNT<='1';
ELSE
CLR_CNT<='0';
END IF;
END PROCESS;
LOAD<=NOT Div2CLK;
TSIEN<=Div2CLK;
END behav;
计数器程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity js is
port(clk,rst,en:in std_logic;
cq:out std_logic_vector(3 downto 0);
cout:out std_logic);
end js;
architecture behav of js is
begin
process(clk,rst,en)
variable cqi:std_logic_vector(3 downto 0);
begin
if rst='1' then cqi:=(others=>'0');
elsif clk'event and clk='1' then
if en='1' then
if cqi<9 then cqi:=cqi+1;
else cqi:=(others=>'0');end if;
end if;
end if;
if cqi=9 then cout<='1';
else cout<='0';end if;
cq<=cqi;
end process;
end behav;
锁存器程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sc IS
PORT(LOAD:IN STD_LOGIC;
DN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END sc;
ARCHITECTURE BEHAV OF sc IS
SIGNAL Q1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(LOAD,Q1)
BEGIN
IF LOAD'EVENT AND LOAD='1' THEN
Q1<=DN;
END IF;
END PROCESS;
DOUT<=Q1;
END BEHAV;
高手指点，谢谢！

Answer 1

是怎么没波形了？ 找不到引脚还是新建的波形文件 仿真不对？，。、
编译通过后是没波形的，得新建一个波形文件， 然后按alt +1看那个 list过滤是不是选的 all。