Question

能帮我写一个VHDL语言么？功能是：四位二进制同步加减可逆计数器。今晚之前能写好么？谢谢！！

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

ENTITY count IS
PORT(clk : in STD_LOGIC;
rst : in std_logic;
change : in STD_LOGIC;
cnt : out STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE behav OF count IS
signal cnt_1:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
PROCESS (clk,rst)
BEGIN
if(rst='1')then
cnt_1<="0000";
elsif(clk'event and clk='1')then
if(change='1')then
cnt_1<=cnt_1+'1';
else
cnt_1<=cnt_1-'1';
end if;
end if;
END PROCESS;
END;