Question

用vhdl文本设计8位全加器？是不是先写半位全加器和全加器的文本，然后设计8

用vhdl文本设计8位全加器？是不是先写半位全加器和全加器的文本，然后设计8位全加器时添加半位和全加器的文件？我只会原理图的设计，文本的设计不会。顺便把设计写一下啊……万分感谢

Answer 1

是的，可以先写出半加器和全加器，然后在组合成八位全加器
半加器描述：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_ADDER IS
PORT (A, B : IN STD_LOGIC;
CO, SO : OUT STD_LOGIC );
END ENTITY H_ADDER;

ARCHITECTURE FH1 OF H_ADDER IS
BEGIN
SO <= NOT (A XOR (NOT B));
CO <= A AND B;
END ARCHITECTURE FH1
全加器的描述：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY F_ADDER IS
PORT (AIN, BIN, CIN : IN STD_LOGIC;
COUT, SUM : OUT STD_LOGIC );
END ENTITY F_ADDER;

ARCHITECTURE FD1 OF F_ADDER IS
COMPONENT H_ADDER IS
PORT (A, B : IN STD_LOGIC;
CO, SO : OUT STD_LOGIC );
END COMPONENT;
SIGNAL D, E, F : STD_LOGIC;
BEGIN
U1 : H_ADDER PORT MAP(A => AIN, B => BIN, CO => D, SO => E);
U2 : H_ADDER PORT MAP(A => E, B => CIN, CO => F, SO => SUM);
COUT <= D OR F;
END ARCHITECTURE FD1;
8位全加器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY F_ADDER8 IS
PORT ( AIN, BIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CIN : IN STD_LOGIC;
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COUT : OUT STD_LOGIC );
END F_ADDER8;

ARCHITECTURE ONE OF F_ADDER8 IS
COMPONENT F_ADDER IS
PORT (AIN, BIN, CIN : IN STD_LOGIC;
COUT, SUM : OUT STD_LOGIC );
END COMPONENT;
SIGNAL C1, C2, C3,C4,C5,C6,C7: STD_LOGIC;
BEGIN
U1 : F_ADDER PORT MAP(AIN => AIN(0), BIN => BIN(0), CIN => CIN, SUM => SUM(0), COUT => C1);
U2 : F_ADDER PORT MAP(AIN => AIN(1), BIN => BIN(1), CIN => C1, SUM => SUM(1), COUT => C2);
U3 : F_ADDER PORT MAP(AIN => AIN(2), BIN => BIN(2), CIN => C2, SUM => SUM(2), COUT => C3);
U4 : F_ADDER PORT MAP(AIN => AIN(3), BIN => BIN(3), CIN => C3, SUM => SUM(3), COUT => C4);
U5 : F_ADDER PORT MAP(AIN => AIN(4), BIN => BIN(4), CIN => C4, SUM => SUM(4), COUT => C5);
U6 : F_ADDER PORT MAP(AIN => AIN(5), BIN => BIN(5), CIN => C5, SUM => SUM(5), COUT => C6);
U7 : F_ADDER PORT MAP(AIN => AIN(6), BIN => BIN(6), CIN => C6, SUM => SUM(6), COUT => C7);
U8 : F_ADDER PORT MAP(AIN => AIN(7), BIN => BIN(7), CIN => C7, SUM => SUM(7), COUT => COUT);

END ONE;