Question

利用vhdl语言和quartus ii6.0设计一个秒表，要有仿真结果

Answer 1

分三个部分：分频器，计数器，译码器。
分频器：library ieee;
use ieee.std_logic_1164.all;
entity eproc is
port(clkin : in std_logic;
clkout : out std_logic
);
end eproc;
architecture behavior of eproc is
signal tmp:std_logic:='0';
signal n:integer range 0 to 479997;
begin
clkout<=tmp;
process(clkin)
begin
if(clkin'event and clkin='1')then
if(n=249999)then
n<=0;
tmp<=not tmp;
else
n<=n+1;
end if;
end if;
end process;
end behavior;
分频器将50MHz的时钟分频为100Hz，每250000次输出翻转一次，实现分频，计数精确到1/100秒。
计数器：library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( CLK : in std_logic;
EN : in std_logic;
CR : in std_logic;
SH,SL,QH,QL : out std_logic_vector(3 downto 0)
);
end counter;
architecture behavior of counter is
signal secH,secL,couH,couL : std_logic_vector(3 downto 0);
begin
process(CR,CLK,EN)
begin
if CR='0' then
couL<="0000";
couH<="0000";
secL<="0000";
secH<="0000";
elsif CLK'event and CLK='1' then
if EN='1' then
if(couL="1001" and couH="1001" and secL="1001" and secH="0101")then
couL<="0000";
couH<="0000";
secL<="0000";
secH<="0000";
elsif(couL="1001" and couH="1001" and secL="1001")then
couL<="0000";
couH<="0000";
secL<="0000";
secH<=secH+1;
elsif(couL="1001" and couH="1001")then
couL<="0000";
couH<="0000";
secL<=secL+1;
secH<=secH;
elsif(couL="1001")then
couL<="0000";
couH<=couH+1;
secL<=secL;
secH<=secH;
else
couL<=couL+1;
end if;
else
couL<=couL;
couH<=couH;
secL<=secL;
secH<=secH;
end if;
end if;
end process;
QL<=couL;
QH<=couH;
SL<=secL;
SH<=secH;
end behavior;
计数器为模6000十进制计数器，计数到5999时四位全部清零；低三位为999时低三位清零，最高位加1；低两位为99时低两位清零，第三位加1；最低位为9时最低位清零，第二位计数加1；否则最低位加1
译码器：library ieee;
use ieee.std_logic_1164.all;
entity bcd is
port(o : in std_logic_vector(3 downto 0);
q : out std_logic_vector(6 downto 0)
);
end bcd;
architecture behavior of bcd is
begin
process(o)
begin
case o is
when"0000"=>
q<="0000001";
when"0001"=>
q<="1001111";
when"0010"=>
q<="0010010";
when"0011"=>
q<="0000110";
when"0100"=>
q<="1001100";
when"0101"=>
q<="0100100";
when"0110"=>
q<="1100000";
when"0111"=>
q<="0001111";
when"1000"=>
q<="0000000";
when"1001"=>
q<="0001100";
when others=>
q<="1111111";
end case;
end process;
end behavior;
译码器为共阳极七段显示数码管的译码，输出低电平有效。
在一个工程里面分别建立以上三个vhd文件，分别进行仿真，生成图形文件，最后打包生成顶层图形文件，锁引脚。
对顶层文件仿真时由于分频太大，无法看到输出波形的变化，建议分别对分频器，计数器，译码器进行仿真。