用maxplus2编译发现一下几个问题,请问可以怎么改?谢了哈
libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt10ispo...
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk_in:in std_logic;k_or,k1,k2:out std_logic);
entity cnt10 is
process(clk,c1)
begin
signal m1,m2:std_logic;
signal c1,c2:std_logic_vector(2 downto 0);
if (c1="001") then m1<=not m1; elsif (c1="011") then m1<=not m1;
if (c1="100") then c1<="000"; else c1<=c1+1; end if;
if rising_enge(clk) then
begin
process(clk,c2)
end process;
end if;
end if;
if (c2="001") then m2<=not m2; elsif (c2="011") then m2<=not m2;
if (c2="100") then c2<="000"; else c2<=c2+1; end if;
if falling_enge(clk) then
begin
k1<=m1; k2<=m2,;k_or<=m1 or m2;
end process;
end if end if;
clk_out<='1';
end bhv;
以上是程序,图片是错误,拜托了 展开
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk_in:in std_logic;k_or,k1,k2:out std_logic);
entity cnt10 is
process(clk,c1)
begin
signal m1,m2:std_logic;
signal c1,c2:std_logic_vector(2 downto 0);
if (c1="001") then m1<=not m1; elsif (c1="011") then m1<=not m1;
if (c1="100") then c1<="000"; else c1<=c1+1; end if;
if rising_enge(clk) then
begin
process(clk,c2)
end process;
end if;
end if;
if (c2="001") then m2<=not m2; elsif (c2="011") then m2<=not m2;
if (c2="100") then c2<="000"; else c2<=c2+1; end if;
if falling_enge(clk) then
begin
k1<=m1; k2<=m2,;k_or<=m1 or m2;
end process;
end if end if;
clk_out<='1';
end bhv;
以上是程序,图片是错误,拜托了 展开
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