Question

基于Verilog FPGA 流水灯设计

要求第一轮间隔0.5秒从led0~led7再回到led0，一共四轮，每经过过一轮增加0.5秒。
只要主程序代码，分频器的代码已经有了。

Answer 1

module first_soft (clk, rst, led);//port
input clk, rst;

output [7:0] led;
reg [7:0] led;
reg [24:0] count;//计数器
reg [24:0] speed;//速度
reg [3:0] state;//状态,[3]=1:正转;[3]=0:翻转;{2,0}速度

always @(posedge clk or negedge rst)//自动变频流水灯
if (!rst)
begin
state<=4'd0;
led<=8'b00000001;
count<=25'd0;
speed<=25'd20000000;

end
else
begin

count<=count+1'b1;
if (count==speed)
begin
count<=25'd0;//计数器复位
if (state[3]==0)//转移发光二极管
begin
led<=led<<1'b1;
if (led==8'b01000000) state[3]<=1'b1;
end
else
begin
led<=led>>1'b1;
if (led==8'b00000010)
begin
case (state[2:0])
3'b000: begin speed<=25'd10000000; state[3:0]<=4'b0001; end
3'b001: begin speed<=25'd5000000; state[3:0]<=4'b0010; end
3'b010: begin speed<=25'd2500000; state[3:0]<=4'b0011; end
3'b011: begin speed<=25'd1200000; state[3:0]<=4'b0100; end
3'b100: begin speed<=25'd2500000; state[3:0]<=4'b0101; end
3'b101: begin speed<=25'd5000000; state[3:0]<=4'b0110; end
3'b110: begin speed<=25'd10000000; state[3:0]<=4'b0111; end
3'b111: begin speed<=25'd20000000; state[3:0]<=4'b0000; end
default: begin speed<=25'd20000000; state[3:0]<=4'b0000; end
endcase
end
end

end

end

endmodule

Answer 2

正转;[3]=0:翻转;{2,0}速度

Answer 3

你是想用LES实现呢还是用NIOS 2实现？

追问

是用FBGA

Answer 4

工作时钟频率多少？

追问

50HZ