你好，请问您可以帮我用VHDL语言设计一个带异步清零和计数使能的8位二进制计数器吗？很急 20
VHDL语言设计一个带异步清零和计数使能的8位二进制计数器源程序如下，程序仿真结果如图所示
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--*-------------------------------------------------------*--
ENTITY counter8 IS
PORT(clk : in std_logic;
clr : in std_logic;
enable : in std_logic;
Q : out std_logic_vector(7 downto 0));
End counter8;
--*------------------------------------------------------*--
ARCHITECTURE arch OF counter8 IS
signal dout : std_logic_vector(7 downto 0);
begin
P1 : process(clk,clr)
begin
if clr='0' then
dout <= "00000000";
elsif clk'event and clk='1' then
if enable='1' then
dout <= dout+1;
elsif enable='0' then
dout <= dout;
end if;
end if;
end process P1;
P2 : process(dout)
begin
Q <= dout;
end process P2;
end arch;
--*-------------------------------------------------------*--
