用VHDL语言如何控制跑马灯的速度?我已经编了一个跑马灯是程序并且可以运行,就是不知道如何控制时间。 10
libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity liushui is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
q1 : out STD_LOGIC;
q2 : out STD_LOGIC;
q3 : out STD_LOGIC;
q4 : out STD_LOGIC;
q5 : out STD_LOGIC;
q6 : out STD_LOGIC;
q7 : out STD_LOGIC;
q8 : out STD_LOGIC);
end liushui;
architecture Behavioral of liushui is
signal q11,q22,q33,q44,q55,q66,q77,q88:std_logic;
signal k: integer range 0 to integer'high;
signal m:integer range 0 to 7;
signal n: integer range 0 to 2;
begin
q1<=q11;
q2<=q22;
q3<=q33;
q4<=q44;
q5<=q55;
q6<=q66;
q7<=q77;
q8<=q88;
process(clk,rst)
begin
if rst='1' then
q11<='0';
q22<='0';
q33<='0';
q44<='0';
q55<='0';
q66<='0';
q77<='0';
q88<='0';
k<=0;
m<=0;
n<=0;
elsif clk'event and clk='1' then
k<=k+1;
if k=12000000 then
if m=7 then
if n=2 then
n<=0;
else
n<=n+1;
m<=0;
end if;
else
m<=m+1;
end if;
k<=0;
end if;
if n=0 then
if m=0 then
q88<='0';
q11<='1';
elsif m=1 then
q11<='0';
q22<='1';
elsif m=2 then
q22<='0';
q33<='1';
elsif m=3 then
q33<='0';
q44<='1';
elsif m=4then
q44<='0';
q55<='1';
elsif m=5 then
q55<='0';
q66<='1';
elsif m=6 then
q66<='0';
q77<='1';
elsif m=7 then
q77<='0';
q88<='1';
end if ;
end if;
if n=1 then
if m=0 then
q77<='0';
q88<='0';
q11<='1';
q22<='1';
elsif m=1 then
q11<='0';
q22<='0';
q33<='1';
q44<='1';
elsif m=2 then
q33<='0';
q44<='0';
q55<='1';
q66<='1';
elsif m=3 then
q55<='0';
q66<='0';
q77<='1';
q88<='1';
elsif m=4 then
q66<='0';
q88<='0';
q11<='1';
q33<='1';
elsif m=5 then
q11<='0';
q33<='0';
q22<='1';
q44<='1';
elsif m=6 then
q22<='0';
q44<='0';
q55<='1';
q77<='1';
elsif m=7 then
q55<='0';
q77<='0';
q66<='1';
q88<='1';
end if;
end if;
if n=2 then
。。。。 end if;
end if;
end if;
end process;
end Behavioral; 展开
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity liushui is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
q1 : out STD_LOGIC;
q2 : out STD_LOGIC;
q3 : out STD_LOGIC;
q4 : out STD_LOGIC;
q5 : out STD_LOGIC;
q6 : out STD_LOGIC;
q7 : out STD_LOGIC;
q8 : out STD_LOGIC);
end liushui;
architecture Behavioral of liushui is
signal q11,q22,q33,q44,q55,q66,q77,q88:std_logic;
signal k: integer range 0 to integer'high;
signal m:integer range 0 to 7;
signal n: integer range 0 to 2;
begin
q1<=q11;
q2<=q22;
q3<=q33;
q4<=q44;
q5<=q55;
q6<=q66;
q7<=q77;
q8<=q88;
process(clk,rst)
begin
if rst='1' then
q11<='0';
q22<='0';
q33<='0';
q44<='0';
q55<='0';
q66<='0';
q77<='0';
q88<='0';
k<=0;
m<=0;
n<=0;
elsif clk'event and clk='1' then
k<=k+1;
if k=12000000 then
if m=7 then
if n=2 then
n<=0;
else
n<=n+1;
m<=0;
end if;
else
m<=m+1;
end if;
k<=0;
end if;
if n=0 then
if m=0 then
q88<='0';
q11<='1';
elsif m=1 then
q11<='0';
q22<='1';
elsif m=2 then
q22<='0';
q33<='1';
elsif m=3 then
q33<='0';
q44<='1';
elsif m=4then
q44<='0';
q55<='1';
elsif m=5 then
q55<='0';
q66<='1';
elsif m=6 then
q66<='0';
q77<='1';
elsif m=7 then
q77<='0';
q88<='1';
end if ;
end if;
if n=1 then
if m=0 then
q77<='0';
q88<='0';
q11<='1';
q22<='1';
elsif m=1 then
q11<='0';
q22<='0';
q33<='1';
q44<='1';
elsif m=2 then
q33<='0';
q44<='0';
q55<='1';
q66<='1';
elsif m=3 then
q55<='0';
q66<='0';
q77<='1';
q88<='1';
elsif m=4 then
q66<='0';
q88<='0';
q11<='1';
q33<='1';
elsif m=5 then
q11<='0';
q33<='0';
q22<='1';
q44<='1';
elsif m=6 then
q22<='0';
q44<='0';
q55<='1';
q77<='1';
elsif m=7 then
q55<='0';
q77<='0';
q66<='1';
q88<='1';
end if;
end if;
if n=2 then
。。。。 end if;
end if;
end if;
end process;
end Behavioral; 展开
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