Question

求学过VHDL语言的大神帮帮忙，quartus ii软件总提示少了分号，不过我一直找不到

代码如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key6 is
port(reset:in std_logic;
key11,key12,key13,key14,key15:in std_logic;
out6:out std_logic_vector(0 downto 3));
end;

architecture bhv of key6 is
signal q:std_logic_vector(0 downto 3);
begin
process(key,reset)
begin
if reset='1' then out6 <= "000000";
elsif (key11=='1') and not (q(0) /='1' and q(1) /='1' and q(2) /='1' and q(3) /='1') then q<="0001";

end if;

end process;
end bhv;

bug如下：Error (10500): VHDL syntax error at key6.vhd(16) near text "="; expecting "(", or an identifier, or unary operator

Answer 1

将if条件中的key11=='1'改成key11='1'。VHDL中没有"=="这个运算符！

Answer 2

elsif 的条件到底是啥，怎么那么乱