求学过VHDL语言的大神帮帮忙，quartus ii软件总提示少了分号，不过我一直找不到
代码如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitykey6...
代码如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key6 is
port(reset:in std_logic;
key11,key12,key13,key14,key15:in std_logic;
out6:out std_logic_vector(0 downto 3));
end;
architecture bhv of key6 is
signal q:std_logic_vector(0 downto 3);
begin
process(key,reset)
begin
if reset='1' then out6 <= "000000";
elsif (key11=='1') and not (q(0) /='1' and q(1) /='1' and q(2) /='1' and q(3) /='1') then q<="0001";
end if;
end process;
end bhv;
bug如下：Error (10500): VHDL syntax error at key6.vhd(16) near text "="; expecting "(", or an identifier, or unary operator 展开
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key6 is
port(reset:in std_logic;
key11,key12,key13,key14,key15:in std_logic;
out6:out std_logic_vector(0 downto 3));
end;
architecture bhv of key6 is
signal q:std_logic_vector(0 downto 3);
begin
process(key,reset)
begin
if reset='1' then out6 <= "000000";
elsif (key11=='1') and not (q(0) /='1' and q(1) /='1' and q(2) /='1' and q(3) /='1') then q<="0001";
end if;
end process;
end bhv;
bug如下：Error (10500): VHDL syntax error at key6.vhd(16) near text "="; expecting "(", or an identifier, or unary operator 展开
展开全部
将if条件中的key11=='1'改成key11='1'。VHDL中没有"=="这个运算符！
本回答由提问者推荐
已赞过
已踩过<
评论
收起
你对这个回答的评价是？
11
2024-11-21 广告
VSIM软件模拟是上海允若信息科技有限公司提供的一项专业服务。我们利用VSIM软件，为客户提供高精度的模拟环境，帮助他们在虚拟空间中测试和验证各种复杂系统。无论是通信系统、网络系统还是其他工程系统，VSIM都能提供详尽的模拟结果，助力客户优...
点击进入详情页
本回答由11提供
推荐律师服务：
若未解决您的问题，请您详细描述您的问题，通过百度律临进行免费专业咨询
