Question

七段数码显示译码器VHDL程序

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seven_seg is
port
(
clk,clr : in std_logic;
dig,seg : out std_logic_vector(7 downto 0)
);
end seven_seg;
architecture rt1 of seven_seg is
signal clk_r:std_logic;
signal scan:std_logic_vector(2 downto 0);
signal dig_r:std_logic_vector(7 downto 0);
signal data_r:std_logic_vector(3 downto 0);
signal seg_r:std_logic_vector(7 downto 0);
begin
dig <= dig_r;
seg <= seg_r;
a:process(clk,clr)
variable count:integer range 0 to 50000000;
begin
if clr = '0' then
count := 0;
elsif clk'event and clk = '1' then
if count = 49999999 then
count := 0;
else
count := count + 1;
end if;
if count <= 24999999 then
clk_r <= '0';
else
clk_r <= '1';
end if;
end if;
end process;
b:process(clk_r,clr)
begin
if clr = '0' then
scan <= "000"冲含;
elsif clk_r'event and clk_r = '1' then
scan <= scan + '1';
end if;
end process;
c:process(scan)
begin
case scan is
when "000" => dig_r <= "11111110"; data_r<="0001";
when "001" => dig_r <= "11111101"; data_r<="0011";
Beijing Universal Pioneering Technology Co.,LTD.
when "010" => dig_r <= "11111011"; data_r<冲判握="0101";
when "011" => dig_r <= "11110111"; data_r<="0111";
when "100" => dig_r <= "11101111"; data_r<="1001";
when "101" => dig_r <= "11011111"; data_r<="1011";
when "110" => dig_r <= "10111111"; data_r<="1101";
when "111" => dig_r <= "01111111"; data_r<="1111";
end case;
end process;
d:process(data_r)
begin
case data_r is
when "0000" => seg_r <= "11000000"散庆;‐‐0
when "0001" => seg_r <= "11111001";‐‐1
when "0010" => seg_r <= "10100100";‐‐2
when "0011" => seg_r <= "10110000";‐‐3
when "0100" => seg_r <= "10011001";‐‐4
when "0101" => seg_r <= "10010010";‐‐5
when "0110" => seg_r <= "10000010";‐‐6
when "0111" => seg_r <= "11111000";‐‐7
when "1000" => seg_r <= "10000000";‐‐8
when "1001" => seg_r <= "10010000";‐‐9
when "1010" => seg_r <= "10001000";‐‐a
when "1011" => seg_r <= "10000011";‐‐b
when "1100" => seg_r <= "10100110";‐‐c
when "1101" => seg_r <= "10100001";‐‐d
when "1110" => seg_r <= "10000110";‐‐e
when "1111" => seg_r <= "10001110";‐‐f
end case;
end process;
end rt1;