modelsim-altera里波形仿真该如何设置啊?
如图 展开
1)新建一个VHDL文件,代码如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYCNT4IS
PORT(CLK:INSTD_LOGIC;
Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCNT4;
ARCHITECTUREBEHOFCNT4IS
SIGNALQ1:STD_LOGIC_VECTOR(3DOWNTO0);BEGIN
PROCESS(CLK)BEGIN
IFCLK'EVENTANDCLK='1'THENQ1<=Q1+1;ENDIF;ENDPROCESS;Q<=Q1;ENDBEH;
2)
按菜单栏Processing|StartCompilation进行编译,也可以按工具栏上的快捷键。编译完,按菜单栏
Processing|Start|StartTestBenchTemplateWriter,成功后,按菜单栏File|Open,打开E:\CNT4\simulation\modelsim\,选择CNT4.vht文件。得到的是testbench文件的一个模板。代码如下:
LIBRARYieee;
USEieee.std_logic_1164.all;
Toplevelmodule
ENTITYCNT4_vhd_tstISENDCNT4_vhd_tst;
ARCHITECTURECNT4_archOFCNT4_vhd_tstIS--constants--signals
SIGNALCLK:STD_LOGIC:='1';
SIGNALQ:STD_LOGIC_VECTOR(3DOWNTO0);COMPONENTCNT4PORT(
CLK:INSTD_LOGIC;
Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;BEGIN
Designinstancename
i1:CNT4PORTMAP(
--listconnectionsbetweenmasterportsandsignalsCLK=>CLK,Q=>Q);
init:PROCESS
--variabledeclarationsBEGIN
--codethatexecutesonlyonce
WAIT;
ENDPROCESSinit;always:PROCESS
--optionalsensitivitylist--(
)
--variabledeclarationsBEGIN
--codeexecutesforeveryeventonsensitivitylistWAIT;
ENDPROCESSalways;ENDCNT4_arch;
做如下修改:
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYCNT4_vhd_tstISENDCNT4_vhd_tst;
ARCHITECTURECNT4_archOFCNT4_vhd_tstIS
--constants--signals
SIGNALCLK:STD_LOGIC:='1';
给时钟信号赋初值
SIGNALQ:STD_LOGIC_VECTOR(3DOWNTO0);COMPONENTCNT4PORT(
CLK:INSTD_LOGIC;
Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;BEGINi1:CNT4PORTMAP(
--listconnectionsbetweenmasterportsandsignalsCLK=>CLK,Q=>Q);
always:PROCESS
--optionalsensitivitylist--(
)
--variabledeclarations
BEGIN
WAITFOR50NS;等待50nsCLK<=NOTCLK;
对时钟信号取反
ENDPROCESSalways;ENDCNT4_arch;
3)保存之后按菜单栏Assignments|Setting,如下图所示。
4)按菜单栏Tools|RunEDASimulation|EDAGateLevelSimulation:
5)等待片刻后会弹出如下窗口,就是模4计数器的波形图。
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不是啊 是modelsim里如何设置波形仿真