Question

请教一个verilog的语法错误

Answer 1

module VrSMex(CLOCK , X , UNLK , HINT);
input CLOCK , X;
output UNLK , HINT;
reg UNLK , HINT;
reg [2:0] Sreg, Snext;
parameter [2:0] A=3'b000,
B=3'b001,
C=3'b010,
D=3'b011,
E=3'b100,
F=3'b101,
G=3'b110,
H=3'b111;
always @ (posedge CLOCK)
Sreg <=Snext;
always @(X , Sreg) begin
case (Sreg)
A: if (X==0) Snext=A;
else Snext=B;
B: if (X==0) Snext=A;
else Snext=C;
C: if (X==0) Snext=D;
else Snext=C;
D: if (X==0) Snext=A;
else Snext=E;
E: if (X==0) Snext=A;
else Snext=F;
F: if (X==0) Snext=A;
else Snext=G;
G: if (X==0) Snext=H;
else Snext=C;
H: if (X==0) Snext=A;
else Snext=E;
default Snext = A;
endcase
end

always @ (X , Sreg) begin
case(Sreg)
A: if(X==0) begin UNLK=0; HINT=0; end
else begin UNLK=0; HINT=1; end
B: if(X==0) begin UNLK=0; HINT=0; end
else begin UNLK=0; HINT=1; end
C: if(X==0) begin UNLK=0; HINT=1; end
else begin UNLK=0; HINT=0; end
D: if(X==0) begin UNLK=0; HINT=0; end
else begin UNLK=0; HINT=1; end
E: if(X==0) begin UNLK=0; HINT=0; end
else begin UNLK=0; HINT=1; end
F: if(X==0) begin UNLK=0; HINT=0; end
else begin UNLK=0; HINT=1; end
G: if(X==0) begin UNLK=0; HINT=1; end
else begin UNLK=0; HINT=0; end
H: if(X==0) begin UNLK=1; HINT=0; end
else begin UNLK=0; HINT=1; end
default begin UNLK=0; HINT=0; end
endcase
end
endmodule

1.两句间用号；用逗号
2. if 面2句要用 BEGIN END 装进

面通程序