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// 你要把那个晶振给我啊,没有它我怎么分频啊,现在我假如您晶振是8M//
module led(clk,rst,led);
input clk,rst;
output [7:0] led;
reg [7:0] led;
//分频产生1s时钟//
reg [23:0] clk1;
always @(posedge clk)
begin
if(clk1==24'd8_000_000)
begin
clk1<=24'd0; led[7]<=~led[7]; led[6]<=~led[6];
end
else
clk1<=clk1+1'd1;
//分频产生0.5s时钟//
reg [23:0] clk2;
always @(posedge clk)
begin
if(clk2==24'd4_000_000)
begin
clk2<=24'd0; led[5]<=~led[5]; led[4]<=~led[4];
end
else
clk2<=clk2+1'd1;
//分频产生0.25s时钟//
reg [23:0] clk3;
always @(posedge clk)
begin
if(clk1==24'd2_000_000)
begin
clk3<=24'd0; led[3]<=~led[3]; led[2]<=~led[2];
end
else
clk3<=clk3+1'd1;
//分频产生0.125s时钟//
reg [23:0] clk4;
always @(posedge clk)
begin
if(clk4==24'd1_000_000)
begin
clk4<=24'd0; led[1]<=~led[1]; led[0]<=~led[0];
end
else
clk4<=clk4+1'd1;
endmodule
module led(clk,rst,led);
input clk,rst;
output [7:0] led;
reg [7:0] led;
//分频产生1s时钟//
reg [23:0] clk1;
always @(posedge clk)
begin
if(clk1==24'd8_000_000)
begin
clk1<=24'd0; led[7]<=~led[7]; led[6]<=~led[6];
end
else
clk1<=clk1+1'd1;
//分频产生0.5s时钟//
reg [23:0] clk2;
always @(posedge clk)
begin
if(clk2==24'd4_000_000)
begin
clk2<=24'd0; led[5]<=~led[5]; led[4]<=~led[4];
end
else
clk2<=clk2+1'd1;
//分频产生0.25s时钟//
reg [23:0] clk3;
always @(posedge clk)
begin
if(clk1==24'd2_000_000)
begin
clk3<=24'd0; led[3]<=~led[3]; led[2]<=~led[2];
end
else
clk3<=clk3+1'd1;
//分频产生0.125s时钟//
reg [23:0] clk4;
always @(posedge clk)
begin
if(clk4==24'd1_000_000)
begin
clk4<=24'd0; led[1]<=~led[1]; led[0]<=~led[0];
end
else
clk4<=clk4+1'd1;
endmodule
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