Question

懂verilog hdl 语言得来 verilog hdl 语言在maxplus2中为什么老有这个错误，帮我看看

module jietiaocunchu(clk2,reset2,enbian,enread,enread1,num,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,a16,a17,a18,a19,a20,
a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31,a32,a33,a34,a35,a36);
input clk2;
// input [5:0] index2;
input reset2;
input enbian;
input enread;
input enread1;
input [3:0] num;
output [3:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,a16,a17,a18,a19,a20,
a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31,a32,a33,a34,a35,a36;

parameter wordwidth=4,memsize=40; //ding yi cun chu qi
reg[wordwidth-1:0] rom[memsize-1:0];
wire [3:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,a16,a17,a18,a19,a20,
a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31,a32,a33,a34,a35,a36;
reg [5:0] index2;

always @ (enbian)
begin
if (!reset2)
//begin
// if (!enread)
// begin
index2<=0;
// end
// end
else
begin
if (!enread)
index2<=0;
else
begin
if (!enread1)
begin
//if (index2>=memsize-1)

// begin // dang cun chu qi man zhi shi cong xin cun cong cun
// index2<=0;
// rom[index2]<=num;

//end
// else
//begin
rom[index2]<=num;
index2<=index2+1;
end

end
end
end

assign a1=rom[0];
assign a2=rom[1];
assign a3=rom[2];
assign a4=rom[3];
assign a5=rom[4];
assign a6=rom[5];
assign a7=rom[6];
assign a8=rom[7];
assign a9=rom[8];
assign a10=rom[9];
assign a11=rom[10];
assign a12=rom[11];
assign a13=rom[12];
assign a14=rom[13];
assign a15=rom[14];
assign a16=rom[15];
assign a17=rom[16];
assign a18=rom[17];
assign a19=rom[18];
assign a20=rom[19];
assign a21=rom[20];
assign a22=rom[21];
assign a23=rom[22];
assign a24=rom[23];
assign a25=rom[24];
assign a26=rom[25];
assign a27=rom[26];
assign a28=rom[27];
assign a29=rom[28];
assign a30=rom[29];
assign a31=rom[30];
assign a32=rom[31];
assign a33=rom[32];
assign a34=rom[33];
assign a35=rom[34];
assign a36=rom[35];

endmodule

错误行reg[wordwidth-1:0] rom[memsize-1:0];
feature error：memory

Answer 1

用的哪块儿芯片，是不是芯片里面没有ROM单元？或者是你这里的数据深度超过了他能提供最大的？
bless

追问

想问下你知道怎么修改吗？应该是没有ROM单元，因为我做的模块程序中只要出现ROM的程序都错误