Question

用quartus2编写的程序出现错误 Error (10170): Verilog HDL syntax error at xxxx.v(1) near text ";"; exp

用quartus2编写的程序出现错误 Error (10170): Verilog HDL syntax error at xxxx.v(1) near text ";"; expecting ".", or an identifier, or "*", or "/"是哪里的问题

Answer 1

出现此错误一般有以下三种情况：
1.某一句代码后面缺少“；”；
2.begin 和end不对应；
3.某一个变量在always语句中等号的左边却没有定义成reg类型。

Answer 2

这样的情况可能是由于你输入法的缘故导致的...也就是符号的全角和半角...

Answer 3

module shi(reset,d5,d6,dw_shi);
output d5,d6;
input reset,dw_shi;
reg[3:0] d5;
reg[1:0] d6;
reg[4:0] count;
always@(posedge reset or posedgedw_shi )
begin
if(reset)
begin
d5<=4'b0;
d6<=2'b0;
count<=5'b0;
end
else
begin
else if(count==5'd23)
count=count+5'b1;
d5<=count%5'd10;
d6<=count/5'd10;
end
end
endmodule
Error (10170): Verilog HDL syntax error at Verilog7.v(17) near text "else"; expecting "end"（大佬们能看看这是错在哪了吗？）

Answer 4

这是代码，有大神帮忙看一下问题出在哪里吗？实在找不出来
library IEEE;
use IEEE.STD_LOGIC_1164. all;
ues IEEE.STD_LOGIC_unsigned. all;
entity show is
port(
clk:in std_logic;
clk011hz£ºbuffer std_logic;
wei: out std_logic_vector(2 downto 0);
duan: out std_logic_vector(7 downto 0)
);
end entity show;
architecture 1xf of show is
signal clt1£ºstd_logic;
signal cnt1:intger range 0 to 1000;
signal cnt2: intger range 0 to 500;
signal yima: std_logic_vector(3 downto 0);
signal count: std_logic_vector(1 downto 0);
begin
process(clk)
begin
if(clk¡¯event and clk=¡¯1¡¯)then
if(cnt1<1000)then cnt1<=cn1+1;
eles
cnt1<=0;clk1<=not clk1;
if count>¡±10¡±then
count<=¡¯00¡¯;
eles
eount<=count+1;
end if;
end if;
end if;
end process;
process(clk1)
begin
if(clk1¡¯event and clk1=¡¯1¡¯)then
if(cnt2<500)then cnt2<=cnt2+1;
eles
cnt2<=0;clk01hz<=not clkj01hz;
end if;
end if;
end process;
process(count,date,yima)
begin
case count is
when ¡°00¡±=>yima<=date(3 downto 0);wei<=¡±001¡±;--1
case yima is

when¡±0000¡±=>duan<=¡°11000000¡±£»--0
when¡±0001¡±=>duan<=¡°11111001¡±£»--1
when¡±0010¡±=>duan<=¡°10100100¡±£»--2
when¡±0011¡±=>duan<=¡°10110000¡±£»--3
when¡±0100¡±=>duan<=¡°10011001¡±£»--4
when¡±0101¡±=>duan<=¡°10010010¡±£»--5
when¡±0110¡±=>duan<=¡°11000010¡±£»--6
when¡±0111¡±=>duan<=¡°11111000¡±£»--7
when¡±1000¡±=>duan<=¡°10000000¡±£»--8
when¡±1001¡±=>duan<=¡°10010000¡±£»--9
WHEN OTHERS=>duan <=¡±11111111¡±;
end case;
when ¡°01¡±=>yima<=date(7 downto 4)£»wei<=¡±010¡±;
case yima is
when¡±0000¡±=>duan<=¡°01000000¡±£»--0
when¡±0001¡±=>duan<=¡°01111001¡±£»--1
when¡±0010¡±=>duan<=¡°00100100¡±£»--2
when¡±0011¡±=>duan<=¡°00110000¡±£»--3
when¡±0100¡±=>duan<=¡°00011001¡±£»--4
when¡±0101¡±=>duan<=¡°00010010¡±£»--5
when¡±0110¡±=>duan<=¡°00000010¡±£»--6
when¡±0111¡±=>duan<=¡°01111000¡±£»--7
when¡±1000¡±=>duan<=¡°00000000¡±£»--8
when¡±1001¡±=>duan<=¡°00010000¡±£»--9
WHEN OTHERS=>duan <=¡±01000000¡±;
end case;
when ¡°10¡±=>yima<=date(11 downto 8)£»wei<=¡±100¡±;
case yima is
when¡±0000¡±=>duan<=¡°11000000¡±£»--0
when¡±0001¡±=>duan<=¡°11111001¡±£»--1
when¡±0010¡±=>duan<=¡°10100100¡±£»--2
when¡±0011¡±=>duan<=¡°10110000¡±£»--3
when¡±0100¡±=>duan<=¡°10011001¡±£»--4
when¡±0101¡±=>duan<=¡°10010010¡±£»--5
when¡±0110¡±=>duan<=¡°11000010¡±£»--6
when¡±0111¡±=>duan<=¡°11111000¡±£»--7
when¡±1000¡±=>duan<=¡°10000000¡±£»--8
when¡±1001¡±=>duan<=¡°10010000¡±£»--9
WHEN OTHERS=>duan <=¡±11111111¡±;
end case;
WHEN OTHERS=>duan <=¡±11111111¡±;
end case;
end process;
end 1xf;

Answer 5

有代码有答案